Hardware Design: SIE
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Hardware Design: SIE Git Source Tree
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Source at commit 717c35e2389243414c45cbefd3f3ed2162dda6cd created 13 years 10 months ago. By Carlos Camargo, Adding post route simulation to FPGA examples | |
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1 | DESIGN = sram_bus |
2 | PINS = sram_bus.ucf |
3 | DEVICE = xc3s250e-VQ100-4 |
4 | BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ |
5 | -g CRC:enable -g StartUpClk:CCLK |
6 | |
7 | SIM_CMD = /opt/cad/modeltech/bin/vsim |
8 | SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do |
9 | SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) |
10 | SAKC_IP = 192.168.254.101 |
11 | |
12 | SRC = sram_bus.v |
13 | |
14 | all: bits |
15 | |
16 | remake: clean-build all |
17 | |
18 | clean: |
19 | rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat |
20 | rm *.bit |
21 | |
22 | clean-build: clean |
23 | rm -rf build |
24 | |
25 | cleanall: clean |
26 | rm -rf build $(DESIGN).bit |
27 | |
28 | bits: $(DESIGN).bit |
29 | |
30 | # |
31 | # Synthesis |
32 | # |
33 | build/project.src: |
34 | @[ -d build ] || mkdir build |
35 | @rm -f $@ |
36 | for i in $(SRC); do echo verilog work ../$$i >> $@; done |
37 | for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done |
38 | |
39 | build/project.xst: build/project.src |
40 | echo "run" > $@ |
41 | echo "-top $(DESIGN) " >> $@ |
42 | echo "-p $(DEVICE)" >> $@ |
43 | echo "-opt_mode Area" >> $@ |
44 | echo "-opt_level 1" >> $@ |
45 | echo "-ifn project.src" >> $@ |
46 | echo "-ifmt mixed" >> $@ |
47 | echo "-ofn project.ngc" >> $@ |
48 | echo "-ofmt NGC" >> $@ |
49 | echo "-rtlview yes" >> $@ |
50 | |
51 | build/project.ngc: build/project.xst $(SRC) |
52 | cd build && xst -ifn project.xst -ofn project.log |
53 | |
54 | build/project.ngd: build/project.ngc $(PINS) |
55 | cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS) |
56 | |
57 | build/project.ncd: build/project.ngd |
58 | cd build && map -pr b -p $(DEVICE) project |
59 | |
60 | build/project_r.ncd: build/project.ncd |
61 | cd build && par -w project project_r.ncd |
62 | |
63 | build/project_r.twr: build/project_r.ncd |
64 | cd build && trce -v 25 project_r.ncd project.pcf |
65 | |
66 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr |
67 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) |
68 | @mv -f build/project_r.bit $@ |
69 | |
70 | build/project_r.v: build/project_r.ncd |
71 | cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v |
72 | |
73 | sim: |
74 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
75 | |
76 | timesim: build/project_r.v |
77 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do |
78 | |
79 | upload: $(DESIGN).bit |
80 | scp $(DESIGN).bit root@$(SAKC_IP): |
81 |
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