Root/Examples/sram/logic/simulation/glbl.v

Source at commit 717c35e2389243414c45cbefd3f3ed2162dda6cd created 13 years 10 months ago.
By Carlos Camargo, Adding post route simulation to FPGA examples
1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11.156.1 2007/03/09 18:12:55 patrickp Exp $
2
3`timescale 1 ps / 1 ps
4
5module glbl ();
6
7    parameter ROC_WIDTH = 100000;
8    parameter TOC_WIDTH = 0;
9
10    wire GSR;
11    wire GTS;
12    wire PRLD;
13
14    reg GSR_int;
15    reg GTS_int;
16    reg PRLD_int;
17
18//-------- JTAG Globals --------------
19    wire JTAG_TDO_GLBL;
20    wire JTAG_TCK_GLBL;
21    wire JTAG_TDI_GLBL;
22    wire JTAG_TMS_GLBL;
23    wire JTAG_TRST_GLBL;
24
25    reg JTAG_CAPTURE_GLBL;
26    reg JTAG_RESET_GLBL;
27    reg JTAG_SHIFT_GLBL;
28    reg JTAG_UPDATE_GLBL;
29
30    reg JTAG_SEL1_GLBL = 0;
31    reg JTAG_SEL2_GLBL = 0 ;
32    reg JTAG_SEL3_GLBL = 0;
33    reg JTAG_SEL4_GLBL = 0;
34
35    reg JTAG_USER_TDO1_GLBL = 1'bz;
36    reg JTAG_USER_TDO2_GLBL = 1'bz;
37    reg JTAG_USER_TDO3_GLBL = 1'bz;
38    reg JTAG_USER_TDO4_GLBL = 1'bz;
39
40    assign (weak1, weak0) GSR = GSR_int;
41    assign (weak1, weak0) GTS = GTS_int;
42    assign (weak1, weak0) PRLD = PRLD_int;
43
44    initial begin
45    GSR_int = 1'b1;
46    PRLD_int = 1'b1;
47    #(ROC_WIDTH)
48    GSR_int = 1'b0;
49    PRLD_int = 1'b0;
50    end
51
52    initial begin
53    GTS_int = 1'b1;
54    #(TOC_WIDTH)
55    GTS_int = 1'b0;
56    end
57
58endmodule
59

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