Root/Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd

Source at commit 717c35e2389243414c45cbefd3f3ed2162dda6cd created 13 years 10 months ago.
By Carlos Camargo, Adding post route simulation to FPGA examples
1library verilog;
2use verilog.vl_types.all;
3entity sram_bus_TB_v is
4    generic(
5        PERIOD : integer := 20;
6        DUTY_CYCLE : real := 0.500000;
7        OFFSET : integer := 0;
8        TSET : integer := 3;
9        THLD : integer := 3;
10        NWS : integer := 3;
11        CAM_OFF : integer := 4000
12    );
13end sram_bus_TB_v;
14

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