Root/plasma/logic/simulation/plasma_TIMING_TB.do

Source at commit 717c35e2389243414c45cbefd3f3ed2162dda6cd created 13 years 10 months ago.
By Carlos Camargo, Adding post route simulation to FPGA examples
1vlib work
2vlog -incr "../build/project.v" "../plasma_TB.v" "glbl.v"
3vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver plasma_TB_v glbl
4view wave
5do wave1.do
6#add wave *
7view structure
8view signals
9run 16us
10

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