Root/Examples/sram_gpio/logic/Makefile

Source at commit acf516e created 13 years 6 months ago.
By Carlos Camargo, Fixing some examples, adding scripts for compiling xilinx libs with ghdl
1DESIGN = sram_bus
2PINS = sram_bus.ucf
3DEVICE = xc3s500e-VQ100-4
4BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
5                  -g CRC:enable -g StartUpClk:CCLK
6
7SIM_CMD = /opt/cad/modeltech/bin/vsim
8SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
9SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
10SAKC_IP = 192.168.254.101
11IVERILOG = iverilog
12XILINXCADROOT = /opt/cad/Xilinx/verilog/src
13#XILINXCADROOT = /opt/cad/modeltech/xilinx/verilog/
14
15
16SRC = sram_bus.v
17
18SIM_SRC = $(DESIGN)_TB.v \
19# sim/unisims/BUFG.v \
20# sim/unisims/DCM.v \
21# sim/unisims/FDDRRSE.v \
22# glbl.v
23# sim/unisims/RAMB16_S2_S9.v
24
25
26all: bits
27
28remake: clean-build all
29
30clean:
31    rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
32    rm -rf *.bit
33
34clean-build: clean
35    rm -rf build
36
37cleanall: clean
38    rm -rf build $(DESIGN).bit
39
40bits: $(DESIGN).bit
41
42#
43# Synthesis
44#
45build/project.src:
46    @[ -d build ] || mkdir build
47    @rm -f $@
48    for i in $(SRC); do echo verilog work ../$$i >> $@; done
49    for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
50
51build/project.xst: build/project.src
52    echo "run" > $@
53    echo "-top $(DESIGN) " >> $@
54    echo "-p $(DEVICE)" >> $@
55    echo "-opt_mode Area" >> $@
56    echo "-opt_level 1" >> $@
57    echo "-ifn project.src" >> $@
58    echo "-ifmt mixed" >> $@
59    echo "-ofn project.ngc" >> $@
60    echo "-ofmt NGC" >> $@
61    echo "-rtlview yes" >> $@
62
63build/project.ngc: build/project.xst $(SRC)
64    cd build && xst -ifn project.xst -ofn project.log
65
66build/project.ngd: build/project.ngc $(PINS)
67    cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
68
69build/project.ncd: build/project.ngd
70    cd build && map -pr b -p $(DEVICE) project
71
72build/project_r.ncd: build/project.ncd
73    cd build && par -w project project_r.ncd
74
75build/project_r.twr: build/project_r.ncd
76    cd build && trce -v 25 project_r.ncd project.pcf
77
78$(DESIGN).bit: build/project_r.ncd build/project_r.twr
79    cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
80    @mv -f build/project_r.bit $@
81
82build/project_r.v: build/project_r.ncd
83    cd build && ngd2ver project.ngd -w project.v
84
85modelsim:
86    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
87
88timesim: build/project_r.v
89    cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
90
91iversim:
92    $(IVERILOG) -Wall -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
93    vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
94    gtkwave simulation/$(DESIGN)_TB.vcd&
95
96upload: $(DESIGN).bit
97    scp $(DESIGN).bit root@$(SAKC_IP):
98

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