Hardware Design: SIE
Sign in or create your account | Project List | Help
Hardware Design: SIE Git Source Tree
Root/
Source at commit acf516e created 13 years 6 months ago. By Carlos Camargo, Fixing some examples, adding scripts for compiling xilinx libs with ghdl | |
---|---|
1 | /**************************************************************************************** |
2 | * |
3 | * Disclaimer This software code and all associated documentation, comments or other |
4 | * of Warranty: information (collectively "Software") is provided "AS IS" without |
5 | * warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY |
6 | * DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED |
7 | * TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES |
8 | * OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT |
9 | * WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE |
10 | * OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. |
11 | * FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR |
12 | * THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, |
13 | * ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE |
14 | * OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, |
15 | * ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, |
16 | * INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, |
17 | * WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, |
18 | * OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE |
19 | * THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH |
20 | * DAMAGES. Because some jurisdictions prohibit the exclusion or |
21 | * limitation of liability for consequential or incidental damages, the |
22 | * above limitation may not apply to you. |
23 | * |
24 | * Copyright 2003 Micron Technology, Inc. All rights reserved. |
25 | * |
26 | ****************************************************************************************/ |
27 | |
28 | // Timing parameters based on Speed Grade |
29 | |
30 | // SYMBOL UNITS DESCRIPTION |
31 | // ------ ----- ----------- |
32 | |
33 | // `ifdef sg6T // Timing Parameters for -6T (CL = 2.5) |
34 | parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time |
35 | parameter tDQSQ = 0.45; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access |
36 | parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time |
37 | parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command |
38 | parameter tRAS = 42.0; // tRAS ns Active to Precharge command time |
39 | parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time |
40 | parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time |
41 | parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time |
42 | parameter tRP = 15.0; // tRP ns Precharge command period |
43 | parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time |
44 | parameter tWR = 15.0; // tWR ns Write recovery time |
45 | |
46 | |
47 | |
48 | // Size Parameters based on Part Width |
49 | |
50 | |
51 | //`else `define x16 |
52 | parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used |
53 | parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used |
54 | parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used |
55 | parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used |
56 | parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used |
57 | |
58 | parameter full_mem_bits = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used |
59 | parameter part_mem_bits = 14; // Set this parameter to control how many unique addresses are used |
60 | |
61 | parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors |
62 | parameter Debug = 1; // Turn on debug message |
63 | |
64 |
Branches:
master