Hardware Design: SIE
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Source at commit acf516e created 13 years 6 months ago. By Carlos Camargo, Fixing some examples, adding scripts for compiling xilinx libs with ghdl | |
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1 | //--------------------------------------------------------------------------- |
2 | // Behavioral model of a static ram chip |
3 | // |
4 | // Organization: |
5 | // |
6 | // 16 bit x 2**(adr_width-1) |
7 | //--------------------------------------------------------------------------- |
8 | module sram16 #( |
9 | parameter adr_width = 18 |
10 | ) ( |
11 | input [adr_width-1:0] adr, |
12 | inout [15:0] dat, |
13 | input ub_n, |
14 | input lb_n, |
15 | input cs_n, |
16 | input we_n, |
17 | input oe_n |
18 | ); |
19 | |
20 | parameter dat_width = 16; |
21 | |
22 | //--------------------------------------------------------------------------- |
23 | // Actual RAM cells |
24 | //--------------------------------------------------------------------------- |
25 | reg [7:0] mem_ub [0:1<<adr_width]; |
26 | reg [7:0] mem_lb [0:1<<adr_width]; |
27 | |
28 | //--------------------------------------------------------------------------- |
29 | // |
30 | //--------------------------------------------------------------------------- |
31 | wire [15:0] mem = { mem_ub[adr], mem_lb[adr] }; |
32 | wire [15:0] zzz = 16'bz; |
33 | |
34 | // Drive output |
35 | assign dat = (!cs_n && !oe_n) ? mem : zzz; |
36 | |
37 | // Write to UB |
38 | always @(*) |
39 | if (!cs_n && !we_n && !ub_n) |
40 | mem_ub[adr] = dat[15:8]; |
41 | |
42 | // Write to LB |
43 | always @(*) |
44 | if (!cs_n && !we_n && !lb_n) |
45 | mem_lb[adr] = dat[7:0]; |
46 | |
47 | always @(*) |
48 | if (!we_n && !oe_n) |
49 | $display("Operational error in RamChip: OE and WE both active"); |
50 | |
51 | endmodule |
52 | |
53 |
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