Hardware Design: SIE
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Source at commit acf516e created 13 years 6 months ago. By Carlos Camargo, Fixing some examples, adding scripts for compiling xilinx libs with ghdl | |
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1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S4.v,v 1.10.158.2 2007/03/09 18:13:18 patrickp Exp $ |
2 | /////////////////////////////////////////////////////////////////////////////// |
3 | // Copyright (c) 1995/2005 Xilinx, Inc. |
4 | // All Right Reserved. |
5 | /////////////////////////////////////////////////////////////////////////////// |
6 | // ____ ____ |
7 | // / /\/ / |
8 | // /___/ \ / Vendor : Xilinx |
9 | // \ \ \/ Version : 8.1i (I.13) |
10 | // \ \ Description : Xilinx Functional Simulation Library Component |
11 | // / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM |
12 | // /___/ /\ Filename : RAMB16_S2_S4.v |
13 | // \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 |
14 | // \___\/\___\ |
15 | // |
16 | // Revision: |
17 | // 03/23/04 - Initial version. |
18 | // End Revision |
19 | |
20 | `ifdef legacy_model |
21 | |
22 | `timescale 1 ps / 1 ps |
23 | |
24 | module RAMB16_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); |
25 | |
26 | parameter INIT_A = 2'h0; |
27 | parameter INIT_B = 4'h0; |
28 | parameter SRVAL_A = 2'h0; |
29 | parameter SRVAL_B = 4'h0; |
30 | parameter WRITE_MODE_A = "WRITE_FIRST"; |
31 | parameter WRITE_MODE_B = "WRITE_FIRST"; |
32 | parameter SIM_COLLISION_CHECK = "ALL"; |
33 | localparam SETUP_ALL = 1000; |
34 | localparam SETUP_READ_FIRST = 3000; |
35 | |
36 | parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
37 | parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
38 | parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
39 | parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
40 | parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
41 | parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
42 | parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
43 | parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
44 | parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
45 | parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
46 | parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
47 | parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
48 | parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
49 | parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
50 | parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
51 | parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
52 | parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
53 | parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
54 | parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
55 | parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
56 | parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
57 | parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
58 | parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
59 | parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
60 | parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
61 | parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
62 | parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
63 | parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
64 | parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
65 | parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
66 | parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
67 | parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
68 | parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
69 | parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
70 | parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
71 | parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
72 | parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
73 | parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
74 | parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
75 | parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
76 | parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
77 | parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
78 | parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
79 | parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
80 | parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
81 | parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
82 | parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
83 | parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
84 | parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
85 | parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
86 | parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
87 | parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
88 | parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
89 | parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
90 | parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
91 | parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
92 | parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
93 | parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
94 | parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
95 | parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
96 | parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
97 | parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
98 | parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
99 | parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
100 | |
101 | output [1:0] DOA; |
102 | reg [1:0] doa_out; |
103 | wire doa_out0, doa_out1; |
104 | |
105 | input [12:0] ADDRA; |
106 | input [1:0] DIA; |
107 | input ENA, CLKA, WEA, SSRA; |
108 | |
109 | output [3:0] DOB; |
110 | reg [3:0] dob_out; |
111 | wire dob_out0, dob_out1, dob_out2, dob_out3; |
112 | |
113 | input [11:0] ADDRB; |
114 | input [3:0] DIB; |
115 | input ENB, CLKB, WEB, SSRB; |
116 | |
117 | reg [18431:0] mem; |
118 | reg [8:0] count; |
119 | reg [1:0] wr_mode_a, wr_mode_b; |
120 | |
121 | reg [5:0] dmi, dbi; |
122 | reg [5:0] pmi, pbi; |
123 | |
124 | wire [12:0] addra_int; |
125 | reg [12:0] addra_reg; |
126 | wire [1:0] dia_int; |
127 | wire ena_int, clka_int, wea_int, ssra_int; |
128 | reg ena_reg, wea_reg, ssra_reg; |
129 | wire [11:0] addrb_int; |
130 | reg [11:0] addrb_reg; |
131 | wire [3:0] dib_int; |
132 | wire enb_int, clkb_int, web_int, ssrb_int; |
133 | reg display_flag; |
134 | reg enb_reg, web_reg, ssrb_reg; |
135 | |
136 | time time_clka, time_clkb; |
137 | time time_clka_clkb; |
138 | time time_clkb_clka; |
139 | |
140 | reg setup_all_a_b; |
141 | reg setup_all_b_a; |
142 | reg setup_zero; |
143 | reg setup_rf_a_b; |
144 | reg setup_rf_b_a; |
145 | reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; |
146 | reg memory_collision, memory_collision_a_b, memory_collision_b_a; |
147 | reg address_collision, address_collision_a_b, address_collision_b_a; |
148 | reg change_clka; |
149 | reg change_clkb; |
150 | |
151 | wire [14:0] data_addra_int; |
152 | wire [14:0] data_addra_reg; |
153 | wire [14:0] data_addrb_int; |
154 | wire [14:0] data_addrb_reg; |
155 | wire [15:0] parity_addra_int; |
156 | wire [15:0] parity_addra_reg; |
157 | wire [15:0] parity_addrb_int; |
158 | wire [15:0] parity_addrb_reg; |
159 | |
160 | tri0 GSR = glbl.GSR; |
161 | |
162 | always @(GSR) |
163 | if (GSR) begin |
164 | assign doa_out = INIT_A[1:0]; |
165 | assign dob_out = INIT_B[3:0]; |
166 | end |
167 | else begin |
168 | deassign doa_out; |
169 | deassign dob_out; |
170 | end |
171 | |
172 | buf b_doa_out0 (doa_out0, doa_out[0]); |
173 | buf b_doa_out1 (doa_out1, doa_out[1]); |
174 | buf b_dob_out0 (dob_out0, dob_out[0]); |
175 | buf b_dob_out1 (dob_out1, dob_out[1]); |
176 | buf b_dob_out2 (dob_out2, dob_out[2]); |
177 | buf b_dob_out3 (dob_out3, dob_out[3]); |
178 | |
179 | buf b_doa0 (DOA[0], doa_out0); |
180 | buf b_doa1 (DOA[1], doa_out1); |
181 | buf b_dob0 (DOB[0], dob_out0); |
182 | buf b_dob1 (DOB[1], dob_out1); |
183 | buf b_dob2 (DOB[2], dob_out2); |
184 | buf b_dob3 (DOB[3], dob_out3); |
185 | |
186 | buf b_addra_0 (addra_int[0], ADDRA[0]); |
187 | buf b_addra_1 (addra_int[1], ADDRA[1]); |
188 | buf b_addra_2 (addra_int[2], ADDRA[2]); |
189 | buf b_addra_3 (addra_int[3], ADDRA[3]); |
190 | buf b_addra_4 (addra_int[4], ADDRA[4]); |
191 | buf b_addra_5 (addra_int[5], ADDRA[5]); |
192 | buf b_addra_6 (addra_int[6], ADDRA[6]); |
193 | buf b_addra_7 (addra_int[7], ADDRA[7]); |
194 | buf b_addra_8 (addra_int[8], ADDRA[8]); |
195 | buf b_addra_9 (addra_int[9], ADDRA[9]); |
196 | buf b_addra_10 (addra_int[10], ADDRA[10]); |
197 | buf b_addra_11 (addra_int[11], ADDRA[11]); |
198 | buf b_addra_12 (addra_int[12], ADDRA[12]); |
199 | buf b_dia_0 (dia_int[0], DIA[0]); |
200 | buf b_dia_1 (dia_int[1], DIA[1]); |
201 | buf b_ena (ena_int, ENA); |
202 | buf b_clka (clka_int, CLKA); |
203 | buf b_ssra (ssra_int, SSRA); |
204 | buf b_wea (wea_int, WEA); |
205 | buf b_addrb_0 (addrb_int[0], ADDRB[0]); |
206 | buf b_addrb_1 (addrb_int[1], ADDRB[1]); |
207 | buf b_addrb_2 (addrb_int[2], ADDRB[2]); |
208 | buf b_addrb_3 (addrb_int[3], ADDRB[3]); |
209 | buf b_addrb_4 (addrb_int[4], ADDRB[4]); |
210 | buf b_addrb_5 (addrb_int[5], ADDRB[5]); |
211 | buf b_addrb_6 (addrb_int[6], ADDRB[6]); |
212 | buf b_addrb_7 (addrb_int[7], ADDRB[7]); |
213 | buf b_addrb_8 (addrb_int[8], ADDRB[8]); |
214 | buf b_addrb_9 (addrb_int[9], ADDRB[9]); |
215 | buf b_addrb_10 (addrb_int[10], ADDRB[10]); |
216 | buf b_addrb_11 (addrb_int[11], ADDRB[11]); |
217 | buf b_dib_0 (dib_int[0], DIB[0]); |
218 | buf b_dib_1 (dib_int[1], DIB[1]); |
219 | buf b_dib_2 (dib_int[2], DIB[2]); |
220 | buf b_dib_3 (dib_int[3], DIB[3]); |
221 | buf b_enb (enb_int, ENB); |
222 | buf b_clkb (clkb_int, CLKB); |
223 | buf b_ssrb (ssrb_int, SSRB); |
224 | buf b_web (web_int, WEB); |
225 | |
226 | initial begin |
227 | for (count = 0; count < 256; count = count + 1) begin |
228 | mem[count] <= INIT_00[count]; |
229 | mem[256 * 1 + count] <= INIT_01[count]; |
230 | mem[256 * 2 + count] <= INIT_02[count]; |
231 | mem[256 * 3 + count] <= INIT_03[count]; |
232 | mem[256 * 4 + count] <= INIT_04[count]; |
233 | mem[256 * 5 + count] <= INIT_05[count]; |
234 | mem[256 * 6 + count] <= INIT_06[count]; |
235 | mem[256 * 7 + count] <= INIT_07[count]; |
236 | mem[256 * 8 + count] <= INIT_08[count]; |
237 | mem[256 * 9 + count] <= INIT_09[count]; |
238 | mem[256 * 10 + count] <= INIT_0A[count]; |
239 | mem[256 * 11 + count] <= INIT_0B[count]; |
240 | mem[256 * 12 + count] <= INIT_0C[count]; |
241 | mem[256 * 13 + count] <= INIT_0D[count]; |
242 | mem[256 * 14 + count] <= INIT_0E[count]; |
243 | mem[256 * 15 + count] <= INIT_0F[count]; |
244 | mem[256 * 16 + count] <= INIT_10[count]; |
245 | mem[256 * 17 + count] <= INIT_11[count]; |
246 | mem[256 * 18 + count] <= INIT_12[count]; |
247 | mem[256 * 19 + count] <= INIT_13[count]; |
248 | mem[256 * 20 + count] <= INIT_14[count]; |
249 | mem[256 * 21 + count] <= INIT_15[count]; |
250 | mem[256 * 22 + count] <= INIT_16[count]; |
251 | mem[256 * 23 + count] <= INIT_17[count]; |
252 | mem[256 * 24 + count] <= INIT_18[count]; |
253 | mem[256 * 25 + count] <= INIT_19[count]; |
254 | mem[256 * 26 + count] <= INIT_1A[count]; |
255 | mem[256 * 27 + count] <= INIT_1B[count]; |
256 | mem[256 * 28 + count] <= INIT_1C[count]; |
257 | mem[256 * 29 + count] <= INIT_1D[count]; |
258 | mem[256 * 30 + count] <= INIT_1E[count]; |
259 | mem[256 * 31 + count] <= INIT_1F[count]; |
260 | mem[256 * 32 + count] <= INIT_20[count]; |
261 | mem[256 * 33 + count] <= INIT_21[count]; |
262 | mem[256 * 34 + count] <= INIT_22[count]; |
263 | mem[256 * 35 + count] <= INIT_23[count]; |
264 | mem[256 * 36 + count] <= INIT_24[count]; |
265 | mem[256 * 37 + count] <= INIT_25[count]; |
266 | mem[256 * 38 + count] <= INIT_26[count]; |
267 | mem[256 * 39 + count] <= INIT_27[count]; |
268 | mem[256 * 40 + count] <= INIT_28[count]; |
269 | mem[256 * 41 + count] <= INIT_29[count]; |
270 | mem[256 * 42 + count] <= INIT_2A[count]; |
271 | mem[256 * 43 + count] <= INIT_2B[count]; |
272 | mem[256 * 44 + count] <= INIT_2C[count]; |
273 | mem[256 * 45 + count] <= INIT_2D[count]; |
274 | mem[256 * 46 + count] <= INIT_2E[count]; |
275 | mem[256 * 47 + count] <= INIT_2F[count]; |
276 | mem[256 * 48 + count] <= INIT_30[count]; |
277 | mem[256 * 49 + count] <= INIT_31[count]; |
278 | mem[256 * 50 + count] <= INIT_32[count]; |
279 | mem[256 * 51 + count] <= INIT_33[count]; |
280 | mem[256 * 52 + count] <= INIT_34[count]; |
281 | mem[256 * 53 + count] <= INIT_35[count]; |
282 | mem[256 * 54 + count] <= INIT_36[count]; |
283 | mem[256 * 55 + count] <= INIT_37[count]; |
284 | mem[256 * 56 + count] <= INIT_38[count]; |
285 | mem[256 * 57 + count] <= INIT_39[count]; |
286 | mem[256 * 58 + count] <= INIT_3A[count]; |
287 | mem[256 * 59 + count] <= INIT_3B[count]; |
288 | mem[256 * 60 + count] <= INIT_3C[count]; |
289 | mem[256 * 61 + count] <= INIT_3D[count]; |
290 | mem[256 * 62 + count] <= INIT_3E[count]; |
291 | mem[256 * 63 + count] <= INIT_3F[count]; |
292 | end |
293 | address_collision <= 0; |
294 | address_collision_a_b <= 0; |
295 | address_collision_b_a <= 0; |
296 | change_clka <= 0; |
297 | change_clkb <= 0; |
298 | data_collision <= 0; |
299 | data_collision_a_b <= 0; |
300 | data_collision_b_a <= 0; |
301 | memory_collision <= 0; |
302 | memory_collision_a_b <= 0; |
303 | memory_collision_b_a <= 0; |
304 | setup_all_a_b <= 0; |
305 | setup_all_b_a <= 0; |
306 | setup_zero <= 0; |
307 | setup_rf_a_b <= 0; |
308 | setup_rf_b_a <= 0; |
309 | end |
310 | |
311 | assign data_addra_int = addra_int * 2; |
312 | assign data_addra_reg = addra_reg * 2; |
313 | assign data_addrb_int = addrb_int * 4; |
314 | assign data_addrb_reg = addrb_reg * 4; |
315 | |
316 | |
317 | initial begin |
318 | |
319 | display_flag = 1; |
320 | |
321 | case (SIM_COLLISION_CHECK) |
322 | |
323 | "NONE" : begin |
324 | assign setup_all_a_b = 1'b0; |
325 | assign setup_all_b_a = 1'b0; |
326 | assign setup_zero = 1'b0; |
327 | assign setup_rf_a_b = 1'b0; |
328 | assign setup_rf_b_a = 1'b0; |
329 | assign display_flag = 0; |
330 | end |
331 | "WARNING_ONLY" : begin |
332 | assign data_collision = 2'b00; |
333 | assign data_collision_a_b = 2'b00; |
334 | assign data_collision_b_a = 2'b00; |
335 | assign memory_collision = 1'b0; |
336 | assign memory_collision_a_b = 1'b0; |
337 | assign memory_collision_b_a = 1'b0; |
338 | end |
339 | "GENERATE_X_ONLY" : begin |
340 | assign display_flag = 0; |
341 | end |
342 | "ALL" : ; |
343 | default : begin |
344 | $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); |
345 | $finish; |
346 | end |
347 | |
348 | endcase // case(SIM_COLLISION_CHECK) |
349 | |
350 | end // initial begin |
351 | |
352 | |
353 | always @(posedge clka_int) begin |
354 | time_clka = $time; |
355 | #0 time_clkb_clka = time_clka - time_clkb; |
356 | change_clka = ~change_clka; |
357 | end |
358 | |
359 | always @(posedge clkb_int) begin |
360 | time_clkb = $time; |
361 | #0 time_clka_clkb = time_clkb - time_clka; |
362 | change_clkb = ~change_clkb; |
363 | end |
364 | |
365 | always @(change_clkb) begin |
366 | if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) |
367 | setup_all_a_b = 1; |
368 | if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) |
369 | setup_rf_a_b = 1; |
370 | end |
371 | |
372 | always @(change_clka) begin |
373 | if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) |
374 | setup_all_b_a = 1; |
375 | if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) |
376 | setup_rf_b_a = 1; |
377 | end |
378 | |
379 | always @(change_clkb or change_clka) begin |
380 | if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) |
381 | setup_zero = 1; |
382 | end |
383 | |
384 | always @(posedge setup_zero) begin |
385 | if ((ena_int == 1) && (wea_int == 1) && |
386 | (enb_int == 1) && (web_int == 1) && |
387 | (data_addra_int[14:2] == data_addrb_int[14:2])) |
388 | memory_collision <= 1; |
389 | end |
390 | |
391 | always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin |
392 | if ((ena_reg == 1) && (wea_reg == 1) && |
393 | (enb_int == 1) && (web_int == 1) && |
394 | (data_addra_reg[14:2] == data_addrb_int[14:2])) |
395 | memory_collision_a_b <= 1; |
396 | end |
397 | |
398 | always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin |
399 | if ((ena_int == 1) && (wea_int == 1) && |
400 | (enb_reg == 1) && (web_reg == 1) && |
401 | (data_addra_int[14:2] == data_addrb_reg[14:2])) |
402 | memory_collision_b_a <= 1; |
403 | end |
404 | |
405 | always @(posedge setup_all_a_b) begin |
406 | if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin |
407 | if ((ena_reg == 1) && (enb_int == 1)) begin |
408 | case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) |
409 | 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
410 | 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
411 | 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end |
412 | // 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
413 | // 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
414 | // 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
415 | 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end |
416 | 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end |
417 | 6'b101011 : begin display_wa_wb; end |
418 | 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
419 | // 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
420 | 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
421 | 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
422 | // 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
423 | 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
424 | 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
425 | // 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
426 | 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
427 | 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
428 | 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
429 | 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
430 | // 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
431 | // 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
432 | // 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
433 | 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
434 | 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
435 | 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
436 | endcase |
437 | end |
438 | end |
439 | setup_all_a_b <= 0; |
440 | end |
441 | |
442 | |
443 | always @(posedge setup_all_b_a) begin |
444 | if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin |
445 | if ((ena_int == 1) && (enb_reg == 1)) begin |
446 | case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) |
447 | 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
448 | // 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
449 | 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end |
450 | 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
451 | // 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
452 | 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end |
453 | 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end |
454 | 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end |
455 | 6'b101011 : begin display_wa_wb; end |
456 | 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
457 | 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
458 | 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
459 | 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
460 | 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
461 | 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
462 | 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
463 | 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
464 | 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
465 | 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
466 | 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
467 | 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
468 | // 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
469 | // 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
470 | // 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
471 | 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
472 | 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
473 | 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
474 | endcase |
475 | end |
476 | end |
477 | setup_all_b_a <= 0; |
478 | end |
479 | |
480 | |
481 | always @(posedge setup_zero) begin |
482 | if (data_addra_int[14:2] == data_addrb_int[14:2]) begin |
483 | if ((ena_int == 1) && (enb_int == 1)) begin |
484 | case ({wr_mode_a, wr_mode_b, wea_int, web_int}) |
485 | 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end |
486 | 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end |
487 | 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end |
488 | 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end |
489 | 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end |
490 | 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end |
491 | 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end |
492 | 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end |
493 | 6'b101011 : begin display_wa_wb; end |
494 | 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end |
495 | // 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end |
496 | 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end |
497 | 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end |
498 | // 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end |
499 | 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end |
500 | 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end |
501 | // 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end |
502 | 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end |
503 | 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end |
504 | 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end |
505 | 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end |
506 | // 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end |
507 | // 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end |
508 | // 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end |
509 | 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end |
510 | 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end |
511 | 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end |
512 | endcase |
513 | end |
514 | end |
515 | setup_zero <= 0; |
516 | end |
517 | |
518 | task display_ra_wb; |
519 | begin |
520 | if (display_flag) |
521 | $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); |
522 | end |
523 | endtask |
524 | |
525 | task display_wa_rb; |
526 | begin |
527 | if (display_flag) |
528 | $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); |
529 | end |
530 | endtask |
531 | |
532 | task display_wa_wb; |
533 | begin |
534 | if (display_flag) |
535 | $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); |
536 | end |
537 | endtask |
538 | |
539 | |
540 | always @(posedge setup_rf_a_b) begin |
541 | if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin |
542 | if ((ena_reg == 1) && (enb_int == 1)) begin |
543 | case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) |
544 | // 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
545 | // 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
546 | // 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
547 | 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
548 | 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
549 | 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end |
550 | // 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
551 | // 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
552 | // 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
553 | // 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
554 | // 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
555 | // 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
556 | // 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
557 | // 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
558 | // 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
559 | // 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
560 | // 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
561 | // 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
562 | // 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
563 | // 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
564 | // 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
565 | 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
566 | 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
567 | 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
568 | // 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
569 | // 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
570 | // 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
571 | endcase |
572 | end |
573 | end |
574 | setup_rf_a_b <= 0; |
575 | end |
576 | |
577 | |
578 | always @(posedge setup_rf_b_a) begin |
579 | if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin |
580 | if ((ena_int == 1) && (enb_reg == 1)) begin |
581 | case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) |
582 | // 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
583 | 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
584 | // 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
585 | // 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
586 | 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
587 | // 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
588 | // 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
589 | 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end |
590 | // 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
591 | // 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
592 | 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
593 | // 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
594 | // 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
595 | 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
596 | // 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
597 | // 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
598 | 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
599 | // 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
600 | // 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
601 | // 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
602 | // 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
603 | // 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
604 | // 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
605 | // 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
606 | // 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
607 | // 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
608 | // 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
609 | endcase |
610 | end |
611 | end |
612 | setup_rf_b_a <= 0; |
613 | end |
614 | |
615 | |
616 | always @(posedge clka_int) begin |
617 | addra_reg <= addra_int; |
618 | ena_reg <= ena_int; |
619 | ssra_reg <= ssra_int; |
620 | wea_reg <= wea_int; |
621 | end |
622 | |
623 | always @(posedge clkb_int) begin |
624 | addrb_reg <= addrb_int; |
625 | enb_reg <= enb_int; |
626 | ssrb_reg <= ssrb_int; |
627 | web_reg <= web_int; |
628 | end |
629 | |
630 | // Data |
631 | always @(posedge memory_collision) begin |
632 | for (dmi = 0; dmi < 2; dmi = dmi + 1) begin |
633 | mem[data_addra_int + dmi] <= 1'bX; |
634 | end |
635 | memory_collision <= 0; |
636 | end |
637 | |
638 | always @(posedge memory_collision_a_b) begin |
639 | for (dmi = 0; dmi < 2; dmi = dmi + 1) begin |
640 | mem[data_addra_reg + dmi] <= 1'bX; |
641 | end |
642 | memory_collision_a_b <= 0; |
643 | end |
644 | |
645 | always @(posedge memory_collision_b_a) begin |
646 | for (dmi = 0; dmi < 2; dmi = dmi + 1) begin |
647 | mem[data_addra_int + dmi] <= 1'bX; |
648 | end |
649 | memory_collision_b_a <= 0; |
650 | end |
651 | |
652 | always @(posedge data_collision[1]) begin |
653 | if (ssra_int == 0) begin |
654 | doa_out <= 2'bX; |
655 | end |
656 | data_collision[1] <= 0; |
657 | end |
658 | |
659 | always @(posedge data_collision[0]) begin |
660 | if (ssrb_int == 0) begin |
661 | for (dbi = 0; dbi < 2; dbi = dbi + 1) begin |
662 | dob_out[data_addra_int[1 : 0] + dbi] <= 1'bX; |
663 | end |
664 | end |
665 | data_collision[0] <= 0; |
666 | end |
667 | |
668 | always @(posedge data_collision_a_b[1]) begin |
669 | if (ssra_reg == 0) begin |
670 | doa_out <= 2'bX; |
671 | end |
672 | data_collision_a_b[1] <= 0; |
673 | end |
674 | |
675 | always @(posedge data_collision_a_b[0]) begin |
676 | if (ssrb_int == 0) begin |
677 | for (dbi = 0; dbi < 2; dbi = dbi + 1) begin |
678 | dob_out[data_addra_reg[1 : 0] + dbi] <= 1'bX; |
679 | end |
680 | end |
681 | data_collision_a_b[0] <= 0; |
682 | end |
683 | |
684 | always @(posedge data_collision_b_a[1]) begin |
685 | if (ssra_int == 0) begin |
686 | doa_out <= 2'bX; |
687 | end |
688 | data_collision_b_a[1] <= 0; |
689 | end |
690 | |
691 | always @(posedge data_collision_b_a[0]) begin |
692 | if (ssrb_reg == 0) begin |
693 | for (dbi = 0; dbi < 2; dbi = dbi + 1) begin |
694 | dob_out[data_addra_int[1 : 0] + dbi] <= 1'bX; |
695 | end |
696 | end |
697 | data_collision_b_a[0] <= 0; |
698 | end |
699 | |
700 | |
701 | initial begin |
702 | case (WRITE_MODE_A) |
703 | "WRITE_FIRST" : wr_mode_a <= 2'b00; |
704 | "READ_FIRST" : wr_mode_a <= 2'b01; |
705 | "NO_CHANGE" : wr_mode_a <= 2'b10; |
706 | default : begin |
707 | $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); |
708 | $finish; |
709 | end |
710 | endcase |
711 | end |
712 | |
713 | initial begin |
714 | case (WRITE_MODE_B) |
715 | "WRITE_FIRST" : wr_mode_b <= 2'b00; |
716 | "READ_FIRST" : wr_mode_b <= 2'b01; |
717 | "NO_CHANGE" : wr_mode_b <= 2'b10; |
718 | default : begin |
719 | $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); |
720 | $finish; |
721 | end |
722 | endcase |
723 | end |
724 | |
725 | // Port A |
726 | always @(posedge clka_int) begin |
727 | if (ena_int == 1'b1) begin |
728 | if (ssra_int == 1'b1) begin |
729 | doa_out[0] <= SRVAL_A[0]; |
730 | doa_out[1] <= SRVAL_A[1]; |
731 | end |
732 | else begin |
733 | if (wea_int == 1'b1) begin |
734 | if (wr_mode_a == 2'b00) begin |
735 | doa_out <= dia_int; |
736 | end |
737 | else if (wr_mode_a == 2'b01) begin |
738 | doa_out[0] <= mem[data_addra_int + 0]; |
739 | doa_out[1] <= mem[data_addra_int + 1]; |
740 | end |
741 | end |
742 | else begin |
743 | doa_out[0] <= mem[data_addra_int + 0]; |
744 | doa_out[1] <= mem[data_addra_int + 1]; |
745 | end |
746 | end |
747 | end |
748 | end |
749 | |
750 | always @(posedge clka_int) begin |
751 | if (ena_int == 1'b1 && wea_int == 1'b1) begin |
752 | mem[data_addra_int + 0] <= dia_int[0]; |
753 | mem[data_addra_int + 1] <= dia_int[1]; |
754 | end |
755 | end |
756 | |
757 | // Port B |
758 | always @(posedge clkb_int) begin |
759 | if (enb_int == 1'b1) begin |
760 | if (ssrb_int == 1'b1) begin |
761 | dob_out[0] <= SRVAL_B[0]; |
762 | dob_out[1] <= SRVAL_B[1]; |
763 | dob_out[2] <= SRVAL_B[2]; |
764 | dob_out[3] <= SRVAL_B[3]; |
765 | end |
766 | else begin |
767 | if (web_int == 1'b1) begin |
768 | if (wr_mode_b == 2'b00) begin |
769 | dob_out <= dib_int; |
770 | end |
771 | else if (wr_mode_b == 2'b01) begin |
772 | dob_out[0] <= mem[data_addrb_int + 0]; |
773 | dob_out[1] <= mem[data_addrb_int + 1]; |
774 | dob_out[2] <= mem[data_addrb_int + 2]; |
775 | dob_out[3] <= mem[data_addrb_int + 3]; |
776 | end |
777 | end |
778 | else begin |
779 | dob_out[0] <= mem[data_addrb_int + 0]; |
780 | dob_out[1] <= mem[data_addrb_int + 1]; |
781 | dob_out[2] <= mem[data_addrb_int + 2]; |
782 | dob_out[3] <= mem[data_addrb_int + 3]; |
783 | end |
784 | end |
785 | end |
786 | end |
787 | |
788 | always @(posedge clkb_int) begin |
789 | if (enb_int == 1'b1 && web_int == 1'b1) begin |
790 | mem[data_addrb_int + 0] <= dib_int[0]; |
791 | mem[data_addrb_int + 1] <= dib_int[1]; |
792 | mem[data_addrb_int + 2] <= dib_int[2]; |
793 | mem[data_addrb_int + 3] <= dib_int[3]; |
794 | end |
795 | end |
796 | |
797 | specify |
798 | (CLKA *> DOA) = (100, 100); |
799 | (CLKB *> DOB) = (100, 100); |
800 | endspecify |
801 | |
802 | endmodule |
803 | |
804 | `else |
805 | |
806 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S4.v,v 1.10.158.2 2007/03/09 18:13:18 patrickp Exp $ |
807 | /////////////////////////////////////////////////////////////////////////////// |
808 | // Copyright (c) 1995/2005 Xilinx, Inc. |
809 | // All Right Reserved. |
810 | /////////////////////////////////////////////////////////////////////////////// |
811 | // ____ ____ |
812 | // / /\/ / |
813 | // /___/ \ / Vendor : Xilinx |
814 | // \ \ \/ Version : 8.1i (I.13) |
815 | // \ \ Description : Xilinx Timing Simulation Library Component |
816 | // / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM |
817 | // /___/ /\ Filename : RAMB16_S2_S4.v |
818 | // \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 |
819 | // \___\/\___\ |
820 | // |
821 | // Revision: |
822 | // 03/23/04 - Initial version. |
823 | // 03/10/05 - Initialized outputs. |
824 | // 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). |
825 | // End Revision |
826 | |
827 | `timescale 1 ps/1 ps |
828 | |
829 | module RAMB16_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); |
830 | |
831 | parameter INIT_A = 2'h0; |
832 | parameter INIT_B = 4'h0; |
833 | parameter SRVAL_A = 2'h0; |
834 | parameter SRVAL_B = 4'h0; |
835 | parameter WRITE_MODE_A = "WRITE_FIRST"; |
836 | parameter WRITE_MODE_B = "WRITE_FIRST"; |
837 | parameter SIM_COLLISION_CHECK = "ALL"; |
838 | localparam SETUP_ALL = 1000; |
839 | localparam SETUP_READ_FIRST = 3000; |
840 | |
841 | parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
842 | parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
843 | parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
844 | parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
845 | parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
846 | parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
847 | parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
848 | parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
849 | parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
850 | parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
851 | parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
852 | parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
853 | parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
854 | parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
855 | parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
856 | parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
857 | parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
858 | parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
859 | parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
860 | parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
861 | parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
862 | parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
863 | parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
864 | parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
865 | parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
866 | parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
867 | parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
868 | parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
869 | parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
870 | parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
871 | parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
872 | parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
873 | parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
874 | parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
875 | parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
876 | parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
877 | parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
878 | parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
879 | parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
880 | parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
881 | parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
882 | parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
883 | parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
884 | parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
885 | parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
886 | parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
887 | parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
888 | parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
889 | parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
890 | parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
891 | parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
892 | parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
893 | parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
894 | parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
895 | parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
896 | parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
897 | parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
898 | parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
899 | parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
900 | parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
901 | parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
902 | parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
903 | parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
904 | parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; |
905 | |
906 | output [1:0] DOA; |
907 | output [3:0] DOB; |
908 | |
909 | input [12:0] ADDRA; |
910 | input [1:0] DIA; |
911 | input ENA, CLKA, WEA, SSRA; |
912 | input [11:0] ADDRB; |
913 | input [3:0] DIB; |
914 | input ENB, CLKB, WEB, SSRB; |
915 | |
916 | reg [1:0] doa_out = INIT_A[1:0]; |
917 | reg [3:0] dob_out = INIT_B[3:0]; |
918 | |
919 | reg [3:0] mem [4095:0]; |
920 | |
921 | reg [8:0] count, countp; |
922 | reg [1:0] wr_mode_a, wr_mode_b; |
923 | |
924 | reg [5:0] dmi, dbi; |
925 | reg [5:0] pmi, pbi; |
926 | |
927 | wire [12:0] addra_int; |
928 | reg [12:0] addra_reg; |
929 | wire [1:0] dia_int; |
930 | wire ena_int, clka_int, wea_int, ssra_int; |
931 | reg ena_reg, wea_reg, ssra_reg; |
932 | wire [11:0] addrb_int; |
933 | reg [11:0] addrb_reg; |
934 | wire [3:0] dib_int; |
935 | wire enb_int, clkb_int, web_int, ssrb_int; |
936 | reg display_flag, output_flag; |
937 | reg enb_reg, web_reg, ssrb_reg; |
938 | |
939 | time time_clka, time_clkb; |
940 | time time_clka_clkb; |
941 | time time_clkb_clka; |
942 | |
943 | reg setup_all_a_b; |
944 | reg setup_all_b_a; |
945 | reg setup_zero; |
946 | reg setup_rf_a_b; |
947 | reg setup_rf_b_a; |
948 | reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; |
949 | reg memory_collision, memory_collision_a_b, memory_collision_b_a; |
950 | reg change_clka; |
951 | reg change_clkb; |
952 | |
953 | wire [14:0] data_addra_int; |
954 | wire [14:0] data_addra_reg; |
955 | wire [14:0] data_addrb_int; |
956 | wire [14:0] data_addrb_reg; |
957 | |
958 | wire dia_enable = ena_int && wea_int; |
959 | wire dib_enable = enb_int && web_int; |
960 | |
961 | tri0 GSR = glbl.GSR; |
962 | wire gsr_int; |
963 | |
964 | buf b_gsr (gsr_int, GSR); |
965 | |
966 | buf b_doa [1:0] (DOA, doa_out); |
967 | buf b_addra [12:0] (addra_int, ADDRA); |
968 | buf b_dia [1:0] (dia_int, DIA); |
969 | buf b_ena (ena_int, ENA); |
970 | buf b_clka (clka_int, CLKA); |
971 | buf b_ssra (ssra_int, SSRA); |
972 | buf b_wea (wea_int, WEA); |
973 | |
974 | buf b_dob [3:0] (DOB, dob_out); |
975 | buf b_addrb [11:0] (addrb_int, ADDRB); |
976 | buf b_dib [3:0] (dib_int, DIB); |
977 | buf b_enb (enb_int, ENB); |
978 | buf b_clkb (clkb_int, CLKB); |
979 | buf b_ssrb (ssrb_int, SSRB); |
980 | buf b_web (web_int, WEB); |
981 | |
982 | |
983 | always @(gsr_int) |
984 | if (gsr_int) begin |
985 | assign {doa_out} = INIT_A; |
986 | assign {dob_out} = INIT_B; |
987 | end |
988 | else begin |
989 | deassign doa_out; |
990 | deassign dob_out; |
991 | end |
992 | |
993 | |
994 | initial begin |
995 | |
996 | for (count = 0; count < 64; count = count + 1) begin |
997 | mem[count] = INIT_00[(count * 4) +: 4]; |
998 | mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; |
999 | mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; |
1000 | mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; |
1001 | mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; |
1002 | mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; |
1003 | mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; |
1004 | mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; |
1005 | mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; |
1006 | mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; |
1007 | mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; |
1008 | mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; |
1009 | mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; |
1010 | mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; |
1011 | mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; |
1012 | mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; |
1013 | mem[64 * 16 + count] = INIT_10[(count * 4) +: 4]; |
1014 | mem[64 * 17 + count] = INIT_11[(count * 4) +: 4]; |
1015 | mem[64 * 18 + count] = INIT_12[(count * 4) +: 4]; |
1016 | mem[64 * 19 + count] = INIT_13[(count * 4) +: 4]; |
1017 | mem[64 * 20 + count] = INIT_14[(count * 4) +: 4]; |
1018 | mem[64 * 21 + count] = INIT_15[(count * 4) +: 4]; |
1019 | mem[64 * 22 + count] = INIT_16[(count * 4) +: 4]; |
1020 | mem[64 * 23 + count] = INIT_17[(count * 4) +: 4]; |
1021 | mem[64 * 24 + count] = INIT_18[(count * 4) +: 4]; |
1022 | mem[64 * 25 + count] = INIT_19[(count * 4) +: 4]; |
1023 | mem[64 * 26 + count] = INIT_1A[(count * 4) +: 4]; |
1024 | mem[64 * 27 + count] = INIT_1B[(count * 4) +: 4]; |
1025 | mem[64 * 28 + count] = INIT_1C[(count * 4) +: 4]; |
1026 | mem[64 * 29 + count] = INIT_1D[(count * 4) +: 4]; |
1027 | mem[64 * 30 + count] = INIT_1E[(count * 4) +: 4]; |
1028 | mem[64 * 31 + count] = INIT_1F[(count * 4) +: 4]; |
1029 | mem[64 * 32 + count] = INIT_20[(count * 4) +: 4]; |
1030 | mem[64 * 33 + count] = INIT_21[(count * 4) +: 4]; |
1031 | mem[64 * 34 + count] = INIT_22[(count * 4) +: 4]; |
1032 | mem[64 * 35 + count] = INIT_23[(count * 4) +: 4]; |
1033 | mem[64 * 36 + count] = INIT_24[(count * 4) +: 4]; |
1034 | mem[64 * 37 + count] = INIT_25[(count * 4) +: 4]; |
1035 | mem[64 * 38 + count] = INIT_26[(count * 4) +: 4]; |
1036 | mem[64 * 39 + count] = INIT_27[(count * 4) +: 4]; |
1037 | mem[64 * 40 + count] = INIT_28[(count * 4) +: 4]; |
1038 | mem[64 * 41 + count] = INIT_29[(count * 4) +: 4]; |
1039 | mem[64 * 42 + count] = INIT_2A[(count * 4) +: 4]; |
1040 | mem[64 * 43 + count] = INIT_2B[(count * 4) +: 4]; |
1041 | mem[64 * 44 + count] = INIT_2C[(count * 4) +: 4]; |
1042 | mem[64 * 45 + count] = INIT_2D[(count * 4) +: 4]; |
1043 | mem[64 * 46 + count] = INIT_2E[(count * 4) +: 4]; |
1044 | mem[64 * 47 + count] = INIT_2F[(count * 4) +: 4]; |
1045 | mem[64 * 48 + count] = INIT_30[(count * 4) +: 4]; |
1046 | mem[64 * 49 + count] = INIT_31[(count * 4) +: 4]; |
1047 | mem[64 * 50 + count] = INIT_32[(count * 4) +: 4]; |
1048 | mem[64 * 51 + count] = INIT_33[(count * 4) +: 4]; |
1049 | mem[64 * 52 + count] = INIT_34[(count * 4) +: 4]; |
1050 | mem[64 * 53 + count] = INIT_35[(count * 4) +: 4]; |
1051 | mem[64 * 54 + count] = INIT_36[(count * 4) +: 4]; |
1052 | mem[64 * 55 + count] = INIT_37[(count * 4) +: 4]; |
1053 | mem[64 * 56 + count] = INIT_38[(count * 4) +: 4]; |
1054 | mem[64 * 57 + count] = INIT_39[(count * 4) +: 4]; |
1055 | mem[64 * 58 + count] = INIT_3A[(count * 4) +: 4]; |
1056 | mem[64 * 59 + count] = INIT_3B[(count * 4) +: 4]; |
1057 | mem[64 * 60 + count] = INIT_3C[(count * 4) +: 4]; |
1058 | mem[64 * 61 + count] = INIT_3D[(count * 4) +: 4]; |
1059 | mem[64 * 62 + count] = INIT_3E[(count * 4) +: 4]; |
1060 | mem[64 * 63 + count] = INIT_3F[(count * 4) +: 4]; |
1061 | end |
1062 | |
1063 | |
1064 | change_clka <= 0; |
1065 | change_clkb <= 0; |
1066 | data_collision <= 0; |
1067 | data_collision_a_b <= 0; |
1068 | data_collision_b_a <= 0; |
1069 | memory_collision <= 0; |
1070 | memory_collision_a_b <= 0; |
1071 | memory_collision_b_a <= 0; |
1072 | setup_all_a_b <= 0; |
1073 | setup_all_b_a <= 0; |
1074 | setup_zero <= 0; |
1075 | setup_rf_a_b <= 0; |
1076 | setup_rf_b_a <= 0; |
1077 | end |
1078 | |
1079 | assign data_addra_int = addra_int * 2; |
1080 | assign data_addra_reg = addra_reg * 2; |
1081 | assign data_addrb_int = addrb_int * 4; |
1082 | assign data_addrb_reg = addrb_reg * 4; |
1083 | |
1084 | |
1085 | initial begin |
1086 | |
1087 | display_flag = 1; |
1088 | output_flag = 1; |
1089 | |
1090 | case (SIM_COLLISION_CHECK) |
1091 | |
1092 | "NONE" : begin |
1093 | output_flag = 0; |
1094 | display_flag = 0; |
1095 | end |
1096 | "WARNING_ONLY" : output_flag = 0; |
1097 | "GENERATE_X_ONLY" : display_flag = 0; |
1098 | "ALL" : ; |
1099 | |
1100 | default : begin |
1101 | $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); |
1102 | $finish; |
1103 | end |
1104 | |
1105 | endcase // case(SIM_COLLISION_CHECK) |
1106 | |
1107 | end // initial begin |
1108 | |
1109 | |
1110 | always @(posedge clka_int) begin |
1111 | if ((output_flag || display_flag)) begin |
1112 | time_clka = $time; |
1113 | #0 time_clkb_clka = time_clka - time_clkb; |
1114 | change_clka = ~change_clka; |
1115 | end |
1116 | end |
1117 | |
1118 | always @(posedge clkb_int) begin |
1119 | if ((output_flag || display_flag)) begin |
1120 | time_clkb = $time; |
1121 | #0 time_clka_clkb = time_clkb - time_clka; |
1122 | change_clkb = ~change_clkb; |
1123 | end |
1124 | end |
1125 | |
1126 | always @(change_clkb) begin |
1127 | if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) |
1128 | setup_all_a_b = 1; |
1129 | if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) |
1130 | setup_rf_a_b = 1; |
1131 | end |
1132 | |
1133 | always @(change_clka) begin |
1134 | if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) |
1135 | setup_all_b_a = 1; |
1136 | if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) |
1137 | setup_rf_b_a = 1; |
1138 | end |
1139 | |
1140 | always @(change_clkb or change_clka) begin |
1141 | if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) |
1142 | setup_zero = 1; |
1143 | end |
1144 | |
1145 | always @(posedge setup_zero) begin |
1146 | if ((ena_int == 1) && (wea_int == 1) && |
1147 | (enb_int == 1) && (web_int == 1) && |
1148 | (data_addra_int[14:2] == data_addrb_int[14:2])) |
1149 | memory_collision <= 1; |
1150 | end |
1151 | |
1152 | always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin |
1153 | if ((ena_reg == 1) && (wea_reg == 1) && |
1154 | (enb_int == 1) && (web_int == 1) && |
1155 | (data_addra_reg[14:2] == data_addrb_int[14:2])) |
1156 | memory_collision_a_b <= 1; |
1157 | end |
1158 | |
1159 | always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin |
1160 | if ((ena_int == 1) && (wea_int == 1) && |
1161 | (enb_reg == 1) && (web_reg == 1) && |
1162 | (data_addra_int[14:2] == data_addrb_reg[14:2])) |
1163 | memory_collision_b_a <= 1; |
1164 | end |
1165 | |
1166 | always @(posedge setup_all_a_b) begin |
1167 | if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin |
1168 | if ((ena_reg == 1) && (enb_int == 1)) begin |
1169 | case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) |
1170 | 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
1171 | 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
1172 | 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end |
1173 | // 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1174 | // 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1175 | // 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1176 | 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end |
1177 | 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end |
1178 | 6'b101011 : begin display_wa_wb; end |
1179 | 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
1180 | // 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1181 | 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
1182 | 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
1183 | // 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1184 | 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
1185 | 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
1186 | // 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1187 | 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end |
1188 | 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1189 | 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1190 | 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1191 | // 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1192 | // 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1193 | // 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1194 | 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1195 | 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1196 | 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1197 | endcase |
1198 | end |
1199 | end |
1200 | setup_all_a_b <= 0; |
1201 | end |
1202 | |
1203 | |
1204 | always @(posedge setup_all_b_a) begin |
1205 | if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin |
1206 | if ((ena_int == 1) && (enb_reg == 1)) begin |
1207 | case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) |
1208 | 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
1209 | // 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1210 | 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end |
1211 | 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
1212 | // 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1213 | 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end |
1214 | 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end |
1215 | 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end |
1216 | 6'b101011 : begin display_wa_wb; end |
1217 | 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1218 | 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1219 | 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1220 | 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1221 | 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1222 | 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1223 | 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1224 | 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1225 | 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1226 | 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
1227 | 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
1228 | 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
1229 | // 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1230 | // 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1231 | // 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1232 | 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
1233 | 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
1234 | 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end |
1235 | endcase |
1236 | end |
1237 | end |
1238 | setup_all_b_a <= 0; |
1239 | end |
1240 | |
1241 | |
1242 | always @(posedge setup_zero) begin |
1243 | if (data_addra_int[14:2] == data_addrb_int[14:2]) begin |
1244 | if ((ena_int == 1) && (enb_int == 1)) begin |
1245 | case ({wr_mode_a, wr_mode_b, wea_int, web_int}) |
1246 | 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end |
1247 | 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end |
1248 | 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end |
1249 | 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end |
1250 | 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end |
1251 | 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end |
1252 | 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end |
1253 | 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end |
1254 | 6'b101011 : begin display_wa_wb; end |
1255 | 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end |
1256 | // 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end |
1257 | 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end |
1258 | 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end |
1259 | // 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end |
1260 | 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end |
1261 | 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end |
1262 | // 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end |
1263 | 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end |
1264 | 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end |
1265 | 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end |
1266 | 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end |
1267 | // 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end |
1268 | // 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end |
1269 | // 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end |
1270 | 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end |
1271 | 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end |
1272 | 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end |
1273 | endcase |
1274 | end |
1275 | end |
1276 | setup_zero <= 0; |
1277 | end |
1278 | |
1279 | task display_ra_wb; |
1280 | begin |
1281 | if (display_flag) |
1282 | $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); |
1283 | end |
1284 | endtask |
1285 | |
1286 | task display_wa_rb; |
1287 | begin |
1288 | if (display_flag) |
1289 | $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); |
1290 | end |
1291 | endtask |
1292 | |
1293 | task display_wa_wb; |
1294 | begin |
1295 | if (display_flag) |
1296 | $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); |
1297 | end |
1298 | endtask |
1299 | |
1300 | |
1301 | always @(posedge setup_rf_a_b) begin |
1302 | if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin |
1303 | if ((ena_reg == 1) && (enb_int == 1)) begin |
1304 | case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) |
1305 | // 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1306 | // 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1307 | // 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1308 | 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
1309 | 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end |
1310 | 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end |
1311 | // 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1312 | // 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1313 | // 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end |
1314 | // 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1315 | // 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1316 | // 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1317 | // 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1318 | // 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1319 | // 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1320 | // 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1321 | // 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1322 | // 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end |
1323 | // 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1324 | // 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1325 | // 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1326 | 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1327 | 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1328 | 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end |
1329 | // 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1330 | // 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1331 | // 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end |
1332 | endcase |
1333 | end |
1334 | end |
1335 | setup_rf_a_b <= 0; |
1336 | end |
1337 | |
1338 | |
1339 | always @(posedge setup_rf_b_a) begin |
1340 | if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin |
1341 | if ((ena_int == 1) && (enb_reg == 1)) begin |
1342 | case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) |
1343 | // 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1344 | 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
1345 | // 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1346 | // 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1347 | 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end |
1348 | // 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1349 | // 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1350 | 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end |
1351 | // 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end |
1352 | // 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
1353 | 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1354 | // 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
1355 | // 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
1356 | 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1357 | // 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
1358 | // 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
1359 | 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end |
1360 | // 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end |
1361 | // 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1362 | // 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1363 | // 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1364 | // 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1365 | // 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1366 | // 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1367 | // 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1368 | // 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1369 | // 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end |
1370 | endcase |
1371 | end |
1372 | end |
1373 | setup_rf_b_a <= 0; |
1374 | end |
1375 | |
1376 | |
1377 | always @(posedge clka_int) begin |
1378 | if ((output_flag || display_flag)) begin |
1379 | addra_reg <= addra_int; |
1380 | ena_reg <= ena_int; |
1381 | ssra_reg <= ssra_int; |
1382 | wea_reg <= wea_int; |
1383 | end |
1384 | end |
1385 | |
1386 | always @(posedge clkb_int) begin |
1387 | if ((output_flag || display_flag)) begin |
1388 | addrb_reg <= addrb_int; |
1389 | enb_reg <= enb_int; |
1390 | ssrb_reg <= ssrb_int; |
1391 | web_reg <= web_int; |
1392 | end |
1393 | end |
1394 | |
1395 | |
1396 | // Data |
1397 | always @(posedge memory_collision) begin |
1398 | if ((output_flag || display_flag)) begin |
1399 | mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; |
1400 | memory_collision <= 0; |
1401 | end |
1402 | |
1403 | end |
1404 | |
1405 | always @(posedge memory_collision_a_b) begin |
1406 | if ((output_flag || display_flag)) begin |
1407 | mem[addra_reg[12:1]][addra_reg[0:0] * 2 +: 2] <= 2'bx; |
1408 | memory_collision_a_b <= 0; |
1409 | end |
1410 | end |
1411 | |
1412 | always @(posedge memory_collision_b_a) begin |
1413 | if ((output_flag || display_flag)) begin |
1414 | mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; |
1415 | memory_collision_b_a <= 0; |
1416 | end |
1417 | end |
1418 | |
1419 | always @(posedge data_collision[1]) begin |
1420 | if (ssra_int == 0 && output_flag) begin |
1421 | doa_out <= #100 2'bX; |
1422 | end |
1423 | data_collision[1] <= 0; |
1424 | end |
1425 | |
1426 | always @(posedge data_collision[0]) begin |
1427 | if (ssrb_int == 0 && output_flag) begin |
1428 | dob_out[addra_int[0:0] * 2 +: 2] <= #100 2'bX; |
1429 | end |
1430 | data_collision[0] <= 0; |
1431 | end |
1432 | |
1433 | always @(posedge data_collision_a_b[1]) begin |
1434 | if (ssra_reg == 0 && output_flag) begin |
1435 | doa_out <= #100 2'bX; |
1436 | end |
1437 | data_collision_a_b[1] <= 0; |
1438 | end |
1439 | |
1440 | always @(posedge data_collision_a_b[0]) begin |
1441 | if (ssrb_int == 0 && output_flag) begin |
1442 | dob_out[addra_reg[0:0] * 2 +: 2] <= #100 2'bX; |
1443 | end |
1444 | data_collision_a_b[0] <= 0; |
1445 | end |
1446 | |
1447 | always @(posedge data_collision_b_a[1]) begin |
1448 | if (ssra_int == 0 && output_flag) begin |
1449 | doa_out <= #100 2'bX; |
1450 | end |
1451 | data_collision_b_a[1] <= 0; |
1452 | end |
1453 | |
1454 | always @(posedge data_collision_b_a[0]) begin |
1455 | if (ssrb_reg == 0 && output_flag) begin |
1456 | dob_out[addra_int[0:0] * 2 +: 2] <= #100 2'bX; |
1457 | end |
1458 | data_collision_b_a[0] <= 0; |
1459 | end |
1460 | |
1461 | |
1462 | initial begin |
1463 | case (WRITE_MODE_A) |
1464 | "WRITE_FIRST" : wr_mode_a <= 2'b00; |
1465 | "READ_FIRST" : wr_mode_a <= 2'b01; |
1466 | "NO_CHANGE" : wr_mode_a <= 2'b10; |
1467 | default : begin |
1468 | $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); |
1469 | $finish; |
1470 | end |
1471 | endcase |
1472 | end |
1473 | |
1474 | initial begin |
1475 | case (WRITE_MODE_B) |
1476 | "WRITE_FIRST" : wr_mode_b <= 2'b00; |
1477 | "READ_FIRST" : wr_mode_b <= 2'b01; |
1478 | "NO_CHANGE" : wr_mode_b <= 2'b10; |
1479 | default : begin |
1480 | $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); |
1481 | $finish; |
1482 | end |
1483 | endcase |
1484 | end |
1485 | |
1486 | |
1487 | // Port A |
1488 | always @(posedge clka_int) begin |
1489 | |
1490 | if (ena_int == 1'b1) begin |
1491 | |
1492 | if (ssra_int == 1'b1) begin |
1493 | {doa_out} <= #100 SRVAL_A; |
1494 | end |
1495 | else begin |
1496 | if (wea_int == 1'b1) begin |
1497 | if (wr_mode_a == 2'b00) begin |
1498 | doa_out <= #100 dia_int; |
1499 | end |
1500 | else if (wr_mode_a == 2'b01) begin |
1501 | |
1502 | doa_out <= #100 mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2]; |
1503 | |
1504 | end |
1505 | end |
1506 | else begin |
1507 | |
1508 | doa_out <= #100 mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2]; |
1509 | |
1510 | end |
1511 | end |
1512 | |
1513 | // memory |
1514 | if (wea_int == 1'b1) begin |
1515 | mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2] <= dia_int; |
1516 | end |
1517 | |
1518 | end |
1519 | end |
1520 | |
1521 | |
1522 | // Port B |
1523 | always @(posedge clkb_int) begin |
1524 | |
1525 | if (enb_int == 1'b1) begin |
1526 | |
1527 | if (ssrb_int == 1'b1) begin |
1528 | {dob_out} <= #100 SRVAL_B; |
1529 | end |
1530 | else begin |
1531 | if (web_int == 1'b1) begin |
1532 | if (wr_mode_b == 2'b00) begin |
1533 | dob_out <= #100 dib_int; |
1534 | end |
1535 | else if (wr_mode_b == 2'b01) begin |
1536 | dob_out <= #100 mem[addrb_int]; |
1537 | end |
1538 | end |
1539 | else begin |
1540 | dob_out <= #100 mem[addrb_int]; |
1541 | end |
1542 | end |
1543 | |
1544 | // memory |
1545 | if (web_int == 1'b1) begin |
1546 | mem[addrb_int] <= dib_int; |
1547 | end |
1548 | |
1549 | end |
1550 | end |
1551 | |
1552 | |
1553 | endmodule |
1554 | |
1555 | `endif |
1556 |
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