Hardware Design: SIE
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Source at commit c48feff62c7e8a7b8a432184839eae88c58f6343 created 13 years 5 months ago. By César Pedraza, .. | |
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1 | -- 07/11/08 |
2 | -- Evalfit_peripheral |
3 | -- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables *** |
4 | -- Funciona hasta con 14 vars. |
5 | -- mapa: |
6 | -- 0 - 0x3F Cromosoma |
7 | -- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB. |
8 | |
9 | |
10 | -- Cromosoma en memoria |
11 | -- bit bit Contenido |
12 | -- 28 a 31 Nivel del arbol |
13 | -- 32 a 47 LUT o tabla del arbol |
14 | -- 48 a 63 Variables de entrada del arbol (4 bits por variable) |
15 | |
16 | library IEEE; |
17 | use IEEE.STD_LOGIC_1164.ALL; |
18 | use IEEE.STD_LOGIC_ARITH.ALL; |
19 | use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating |
20 | ---- any Xilinx primitives in this code. |
21 | library UNISIM; |
22 | use UNISIM.VComponents.all; |
23 | |
24 | entity evalfit_peripheral is |
25 | Port ( clk, reset, habilita: in STD_LOGIC; |
26 | maxcombs : in STD_LOGIC_VECTOR (0 to 15); |
27 | nivel_max : in STD_LOGIC_VECTOR (0 to 3); |
28 | peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63); |
29 | peripheral_mem_en : out std_logic; |
30 | peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63); |
31 | peripheral_mem_we : out STD_LOGIC; |
32 | peripheral_mem_addr : out STD_LOGIC_VECTOR (0 to 8); |
33 | evalfit3_estado : out std_logic_vector(0 to 7); |
34 | errores : out STD_LOGIC_VECTOR (0 to 15); |
35 | fin_ack : out std_logic; |
36 | reg0_s : out STD_LOGIC_VECTOR (0 to 31); |
37 | reg1_s : out STD_LOGIC_VECTOR (0 to 31); |
38 | reg2_s : out STD_LOGIC_VECTOR (0 to 31); |
39 | reg3_s : out STD_LOGIC_VECTOR (0 to 31); |
40 | reg4_s : out STD_LOGIC_VECTOR (0 to 31) |
41 | ); |
42 | end evalfit_peripheral; |
43 | |
44 | architecture Behavioral of evalfit_peripheral is |
45 | |
46 | function mux16(sel: in std_logic_vector(0 to 3); ent: in std_logic_vector(0 to 15)) return std_logic is |
47 | begin |
48 | case sel is |
49 | when "0000" => return ent(15); |
50 | when "0001" => return ent(14); |
51 | when "0010" => return ent(13); |
52 | when "0011" => return ent(12); |
53 | when "0100" => return ent(11); |
54 | when "0101" => return ent(10); |
55 | when "0110" => return ent(9); |
56 | when "0111" => return ent(8); |
57 | when "1000" => return ent(7); |
58 | when "1001" => return ent(6); |
59 | when "1010" => return ent(5); |
60 | when "1011" => return ent(4); |
61 | when "1100" => return ent(3); |
62 | when "1101" => return ent(2); |
63 | when "1110" => return ent(1); |
64 | when others => return ent(0); |
65 | end case; |
66 | end mux16; |
67 | |
68 | function mux4(sel: in std_logic_vector(0 to 1); ent: in std_logic_vector(0 to 3)) return std_logic is |
69 | begin |
70 | case sel is |
71 | when "00" => return ent(3); |
72 | when "01" => return ent(2); |
73 | when "10" => return ent(1); |
74 | when others => return ent(0); |
75 | end case; |
76 | end mux4; |
77 | |
78 | -- senales para evaluar funciones |
79 | signal reg0, reg1, reg2, reg3, reg4, regn3, regn4:STD_LOGIC_VECTOR (0 to 31); |
80 | signal reg0_sig, reg1_sig, reg2_sig, reg3_sig, reg4_sig, regn3_sig, regn4_sig :STD_LOGIC_VECTOR (0 to 31); |
81 | signal sel_aux0, sel_aux1, sel_aux2, sel_aux3, sel_aux4, sel_auxn3, sel_auxn4, sal_arbol, minter_n3, minter_n4 : std_logic_vector(0 to 3); |
82 | signal salida_s, fin_ack_sig, fifow_wrreq_sig: std_logic; |
83 | signal entrada, errores_aux, errores_sig, salida_nivel : STD_LOGIC_VECTOR (0 to 15); |
84 | |
85 | -- senales para las memorias, guardan resultados de arboles intermedios |
86 | signal DO_n2, DI_n2, DO_n3, DI_n3, DO_n4, DI_n4: std_logic_vector(3 downto 0); |
87 | signal ADDR_n2, ADDR_n3, ADDR_n4: std_logic_vector(0 to 13); |
88 | signal WE_n2, WE_n3, WE_n4: std_logic_vector(3 downto 0); |
89 | signal WE_n2_sig, WE_n3_sig, WE_n4_sig: std_logic_vector(3 downto 0); |
90 | signal EN_n2, SSR, EN_n3, EN_n4: std_logic; |
91 | |
92 | -- senales para el control |
93 | type estado is (reset1, reset2, inicio, proceso, n1, n2, n3, n4, precuenta, cuenta, final, final2); |
94 | signal ep, es: estado; |
95 | signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3); |
96 | signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1); |
97 | signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15); |
98 | signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 7); |
99 | signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8); |
100 | |
101 | begin |
102 | |
103 | |
104 | process(ep, habilita, reg0, reg1, reg2, reg3, reg4, regn3, regn4, nivel, c1, c2, c3, c4, conta, |
105 | salida_s, salida_nivel, WE_n2, WE_n3, WE_n4, nivel_max, |
106 | maxcombs, peripheral_mem_in, peripheral_mem_addr_crom, peripheral_mem_addr_aux) |
107 | begin |
108 | es <= reset1; |
109 | WE_n2_sig <= "0000"; |
110 | WE_n3_sig <= "0000"; |
111 | WE_n4_sig <= "0000"; |
112 | reg0_sig <= reg0; |
113 | reg1_sig <= reg1; |
114 | reg2_sig <= reg2; |
115 | reg3_sig <= reg3; |
116 | reg4_sig <= reg4; |
117 | regn3_sig <= regn3; |
118 | regn4_sig <= regn4; |
119 | conta_sig <= conta; |
120 | conta2_sig <= conta2; |
121 | c1_sig <= c1; |
122 | c2_sig <= c2; |
123 | c3_sig <= c3; |
124 | c4_sig <= c4; |
125 | DI_n2 <= "0000"; |
126 | DI_n3 <= "0000"; |
127 | DI_n4 <= "0000"; |
128 | fin_ack_sig <= '0'; |
129 | peripheral_mem_addr_sig <= peripheral_mem_addr_aux; |
130 | peripheral_mem_addr_crom_sig <= peripheral_mem_addr_crom; |
131 | peripheral_mem_we <= '0'; |
132 | peripheral_mem_en <= '0'; |
133 | errores_sig <= errores_aux; |
134 | nivel_sig <= nivel_reg; |
135 | estado_evalf3_sig <= x"FF"; |
136 | case ep is |
137 | when reset1 => --poner la memoria a 0000 |
138 | WE_n2_sig <= "1111"; |
139 | WE_n3_sig <= "1111"; |
140 | WE_n4_sig <= "1111"; |
141 | conta2_sig <= (others => '0'); |
142 | es <= reset2; |
143 | when reset2 => |
144 | DI_n2 <= "0000"; |
145 | DI_n3 <= "0000"; |
146 | DI_n4 <= "0000"; |
147 | if(conta2 = maxcombs)then |
148 | WE_n2_sig <= "0000"; |
149 | WE_n3_sig <= "0000"; |
150 | WE_n4_sig <= "0000"; |
151 | conta2_sig <= (others => '0'); |
152 | es <= inicio; |
153 | else |
154 | WE_n2_sig <= "1111"; |
155 | WE_n3_sig <= "1111"; |
156 | WE_n4_sig <= "1111"; |
157 | conta2_sig <= conta2 + 1; |
158 | es <= reset2; |
159 | end if; |
160 | |
161 | when inicio => |
162 | if(habilita = '0') then |
163 | es <= inicio; |
164 | conta_sig <= (others => '0'); |
165 | conta2_sig <= (others => '0'); |
166 | peripheral_mem_addr_sig <= (others => '0'); |
167 | c1_sig <= "00"; |
168 | c2_sig <= "00"; |
169 | c3_sig <= "00"; |
170 | c4_sig <= "00"; |
171 | errores_sig <= x"0000"; |
172 | else |
173 | es <= proceso; |
174 | peripheral_mem_en <= '1'; |
175 | end if; |
176 | estado_evalf3_sig <= x"01"; |
177 | |
178 | when proceso => |
179 | peripheral_mem_en <= '1'; |
180 | if(nivel = "0001")then |
181 | case c1 is |
182 | when "00" => reg0_sig <= peripheral_mem_in(32 to 63); |
183 | when "01" => reg1_sig <= peripheral_mem_in(32 to 63); |
184 | when "10" => reg2_sig <= peripheral_mem_in(32 to 63); |
185 | when others => reg3_sig <= peripheral_mem_in(32 to 63); |
186 | end case; |
187 | es <= n1; |
188 | elsif(nivel = "0010")then |
189 | reg4_sig <= peripheral_mem_in(32 to 63); |
190 | WE_n2_sig(conv_integer(c2)) <= '1'; |
191 | DI_n2(conv_integer(c2)) <= salida_nivel(2); |
192 | es <= n2; |
193 | elsif(nivel = "0011")then |
194 | regn3_sig <= peripheral_mem_in(32 to 63); |
195 | WE_n3_sig(conv_integer(c3)) <= '1'; |
196 | DI_n3(conv_integer(c3)) <= salida_nivel(3); |
197 | es <= n3; |
198 | elsif(nivel = "0100")then |
199 | regn4_sig <= peripheral_mem_in(32 to 63); |
200 | WE_n4_sig(conv_integer(c4)) <= '1'; |
201 | DI_n4(conv_integer(c4)) <= salida_nivel(4); |
202 | es <= n4; |
203 | elsif(nivel = "1111")then |
204 | es <= final2; |
205 | end if; |
206 | peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1; |
207 | peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1; |
208 | nivel_sig <= nivel; |
209 | estado_evalf3_sig <= x"02"; |
210 | |
211 | when n1 => |
212 | peripheral_mem_en <= '1'; |
213 | c1_sig <= c1 + 1; |
214 | peripheral_mem_addr_sig <= peripheral_mem_addr_aux; |
215 | es <= proceso; |
216 | estado_evalf3_sig <= x"03"; |
217 | |
218 | when n2 => |
219 | WE_n2_sig(conv_integer(c2)) <= '1'; |
220 | DI_n2(conv_integer(c2)) <= salida_nivel(2); |
221 | peripheral_mem_en <= '1'; |
222 | peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida |
223 | es <= precuenta; |
224 | conta2_sig <= (others => '0'); |
225 | estado_evalf3_sig <= x"04"; |
226 | |
227 | when n3 => |
228 | WE_n3_sig(conv_integer(c3)) <= '1'; |
229 | DI_n3(conv_integer(c3)) <= salida_nivel(3); |
230 | peripheral_mem_en <= '1'; |
231 | peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- |
232 | es <= precuenta; |
233 | conta2_sig <= (others => '0'); |
234 | estado_evalf3_sig <= x"05"; |
235 | |
236 | when n4 => |
237 | WE_n4_sig(conv_integer(c4)) <= '1'; |
238 | DI_n4(conv_integer(c4)) <= salida_nivel(4); |
239 | peripheral_mem_en <= '1'; |
240 | peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- |
241 | es <= precuenta; |
242 | conta2_sig <= (others => '0'); |
243 | estado_evalf3_sig <= x"06"; |
244 | |
245 | when precuenta => |
246 | WE_n2_sig <= WE_n2; |
247 | WE_n3_sig <= WE_n3; |
248 | WE_n4_sig <= WE_n4; |
249 | DI_n2(conv_integer(c2)) <= salida_nivel(2); |
250 | DI_n3(conv_integer(c3)) <= salida_nivel(3); |
251 | DI_n4(conv_integer(c4)) <= salida_nivel(4); |
252 | peripheral_mem_en <= '1'; |
253 | peripheral_mem_addr_sig <= "001000000" + ('0' & conta2(2 to 9)); |
254 | conta_sig <= conta; |
255 | conta2_sig <= conta + 1; |
256 | es <= cuenta; |
257 | estado_evalf3_sig <= x"07"; |
258 | |
259 | when cuenta => |
260 | DI_n2(conv_integer(c2)) <= salida_nivel(2); |
261 | DI_n3(conv_integer(c3)) <= salida_nivel(3); |
262 | DI_n4(conv_integer(c4)) <= salida_nivel(4); |
263 | peripheral_mem_en <= '1'; |
264 | if(conta = maxcombs)then |
265 | WE_n2_sig <= "0000"; |
266 | WE_n3_sig <= "0000"; |
267 | WE_n4_sig <= "0000"; |
268 | conta_sig <= (others => '0'); |
269 | conta2_sig <= (others => '0'); |
270 | peripheral_mem_addr_sig <= peripheral_mem_addr_crom; --direccion de mem donde esta el cromosoma |
271 | es <= final; |
272 | else |
273 | WE_n2_sig <= WE_n2; |
274 | WE_n3_sig <= WE_n3; |
275 | WE_n4_sig <= WE_n4; |
276 | conta_sig <= conta + 1; |
277 | conta2_sig <= conta2 + 1; |
278 | peripheral_mem_addr_sig <= "001000000" + ('0' & conta2(2 to 9));--crear señal conta futura |
279 | if(conta(10 to 15) = "111111")then |
280 | es <= precuenta; |
281 | else |
282 | es <= cuenta; |
283 | end if; |
284 | end if; |
285 | if(nivel_reg = nivel_max)then |
286 | if(salida_nivel(conv_integer(nivel_max)) = peripheral_mem_in(conv_integer(conta(10 to 15))))then |
287 | errores_sig <= errores_aux; |
288 | else |
289 | errores_sig <= errores_aux + 1; |
290 | end if; |
291 | else |
292 | errores_sig <= errores_aux; |
293 | end if; |
294 | |
295 | estado_evalf3_sig <= x"08"; |
296 | |
297 | when final => |
298 | if(nivel_reg = "0010")then |
299 | c2_sig <= c2 + 1; |
300 | elsif(nivel_reg = "0011")then |
301 | c3_sig <= c3 + 1; |
302 | elsif(nivel_reg = "0100")then |
303 | c4_sig <= c4 + 1; |
304 | end if; |
305 | peripheral_mem_en <= '1'; |
306 | peripheral_mem_addr_sig <= peripheral_mem_addr_crom; |
307 | es <= proceso; |
308 | estado_evalf3_sig <= x"09"; |
309 | |
310 | when final2 => |
311 | if(habilita = '1') then |
312 | es <= final2; |
313 | else |
314 | es <= inicio; |
315 | end if; |
316 | fin_ack_sig <= '1'; |
317 | estado_evalf3_sig <= x"0A"; |
318 | when others => es <= inicio; |
319 | |
320 | end case; |
321 | end process; |
322 | |
323 | |
324 | process(clk, reset) |
325 | begin |
326 | if(reset = '1')then |
327 | ep <= reset1; |
328 | c1 <= "00"; |
329 | c2 <= "00"; |
330 | c3 <= "00"; |
331 | c4 <= "00"; |
332 | WE_n2 <= "0000"; |
333 | WE_n3 <= "0000"; |
334 | WE_n4 <= "0000"; |
335 | reg0 <= x"00000000"; |
336 | reg1 <= x"00000000"; |
337 | reg2 <= x"00000000"; |
338 | reg3 <= x"00000000"; |
339 | reg4 <= x"00000000"; |
340 | regn3 <= x"00000000"; |
341 | regn4 <= x"00000000"; |
342 | conta <= (others => '0'); |
343 | conta2 <= (others => '0'); |
344 | fin_ack <= '0'; |
345 | peripheral_mem_addr_aux <= "000000000"; |
346 | peripheral_mem_addr_crom <= "000000000"; |
347 | errores_aux <= (others => '0'); |
348 | nivel_reg <= "0000"; |
349 | estado_evalf3 <= x"00"; |
350 | elsif(rising_edge(clk))then |
351 | ep <= es; |
352 | c1 <= c1_sig; |
353 | c2 <= c2_sig; |
354 | c3 <= c3_sig; |
355 | c4 <= c4_sig; |
356 | WE_n2 <= WE_n2_sig; |
357 | WE_n3 <= WE_n3_sig; |
358 | WE_n4 <= WE_n4_sig; |
359 | reg0 <= reg0_sig; |
360 | reg1 <= reg1_sig; |
361 | reg2 <= reg2_sig; |
362 | reg3 <= reg3_sig; |
363 | reg4 <= reg4_sig; |
364 | regn3 <= regn3_sig; |
365 | regn4 <= regn4_sig; |
366 | conta <= conta_sig; |
367 | conta2 <= conta2_sig; |
368 | fin_ack <= fin_ack_sig; |
369 | peripheral_mem_addr_aux <= peripheral_mem_addr_sig; |
370 | peripheral_mem_addr_crom <= peripheral_mem_addr_crom_sig; |
371 | errores_aux <= errores_sig; |
372 | nivel_reg <= nivel_sig; |
373 | estado_evalf3 <= estado_evalf3_sig; |
374 | end if; |
375 | end process; |
376 | |
377 | process(nivel_reg, conta, conta2) |
378 | begin |
379 | case nivel_reg is |
380 | when "0000" => |
381 | ADDR_n2 <= conta(2 to 15); |
382 | ADDR_n3 <= conta(2 to 15); |
383 | ADDR_n4 <= conta(2 to 15); |
384 | when "0010" => |
385 | ADDR_n2 <= conta(2 to 15); |
386 | ADDR_n3 <= conta(2 to 15); |
387 | ADDR_n4 <= conta(2 to 15); |
388 | when "0011" => |
389 | ADDR_n2 <= conta2(2 to 15); |
390 | ADDR_n3 <= conta(2 to 15); |
391 | ADDR_n4 <= conta(2 to 15); |
392 | when "0100" => |
393 | ADDR_n2 <= conta(2 to 15); |
394 | ADDR_n3 <= conta2(2 to 15); |
395 | ADDR_n4 <= conta(2 to 15); |
396 | when others => |
397 | ADDR_n2 <= conta2(2 to 15); |
398 | ADDR_n3 <= conta2(2 to 15); |
399 | ADDR_n4 <= conta2(2 to 15); |
400 | end case; |
401 | |
402 | end process; |
403 | |
404 | |
405 | errores <= errores_aux; |
406 | peripheral_mem_addr <= peripheral_mem_addr_aux; |
407 | nivel <= peripheral_mem_in(28 to 31); |
408 | EN_n2 <= '1'; |
409 | EN_n3 <= '1'; |
410 | EN_n4 <= '1'; |
411 | SSR <= '0'; |
412 | minter_n3 <= DO_n2; |
413 | minter_n4 <= DO_n3; |
414 | entrada <= conta; |
415 | |
416 | evalfit3_estado <= estado_evalf3; |
417 | reg0_s <= reg0; |
418 | reg1_s <= reg1; |
419 | reg2_s <= reg2; |
420 | reg3_s <= reg3; |
421 | reg4_s <= reg4; |
422 | salida_nivel(1) <= sal_arbol(3); |
423 | |
424 | sel_aux0(3) <= mux16(reg0(28 to 31), entrada); |
425 | sel_aux0(2) <= mux16(reg0(24 to 27), entrada); |
426 | sel_aux0(1) <= mux16(reg0(20 to 23), entrada); |
427 | sel_aux0(0) <= mux16(reg0(16 to 19), entrada); |
428 | sal_arbol(3) <= mux16(sel_aux0, reg0(0 to 15)); -- reg0(0 to 15) = dato_lut |
429 | |
430 | sel_aux1(3) <= mux16(reg1(28 to 31), entrada); |
431 | sel_aux1(2) <= mux16(reg1(24 to 27), entrada); |
432 | sel_aux1(1) <= mux16(reg1(20 to 23), entrada); |
433 | sel_aux1(0) <= mux16(reg1(16 to 19), entrada); |
434 | sal_arbol(2) <= mux16(sel_aux1, reg1(0 to 15)); |
435 | |
436 | sel_aux2(3) <= mux16(reg2(28 to 31), entrada); |
437 | sel_aux2(2) <= mux16(reg2(24 to 27), entrada); |
438 | sel_aux2(1) <= mux16(reg2(20 to 23), entrada); |
439 | sel_aux2(0) <= mux16(reg2(16 to 19), entrada); |
440 | sal_arbol(1) <= mux16(sel_aux2, reg2(0 to 15)); |
441 | |
442 | sel_aux3(3) <= mux16(reg3(28 to 31), entrada); |
443 | sel_aux3(2) <= mux16(reg3(24 to 27), entrada); |
444 | sel_aux3(1) <= mux16(reg3(20 to 23), entrada); |
445 | sel_aux3(0) <= mux16(reg3(16 to 19), entrada); |
446 | sal_arbol(0) <= mux16(sel_aux3, reg3(0 to 15)); |
447 | |
448 | sel_aux4(3) <= mux4(reg4(30 to 31), sal_arbol); --arbol de 2do nivel |
449 | sel_aux4(2) <= mux4(reg4(26 to 27), sal_arbol); |
450 | sel_aux4(1) <= mux4(reg4(22 to 23), sal_arbol); |
451 | sel_aux4(0) <= mux4(reg4(18 to 19), sal_arbol); |
452 | salida_nivel(2) <= mux16(sel_aux4, reg4(0 to 15)); |
453 | |
454 | sel_auxn3(3) <= mux4(regn3(30 to 31), minter_n3); --arboles de 3er nivel |
455 | sel_auxn3(2) <= mux4(regn3(26 to 27), minter_n3); |
456 | sel_auxn3(1) <= mux4(regn3(22 to 23), minter_n3); |
457 | sel_auxn3(0) <= mux4(regn3(18 to 19), minter_n3); |
458 | salida_nivel(3) <= mux16(sel_auxn3, regn3(0 to 15)); |
459 | |
460 | sel_auxn4(3) <= mux4(regn4(30 to 31), minter_n4); --arboles de 4to nivel |
461 | sel_auxn4(2) <= mux4(regn4(26 to 27), minter_n4); |
462 | sel_auxn4(1) <= mux4(regn4(22 to 23), minter_n4); |
463 | sel_auxn4(0) <= mux4(regn4(18 to 19), minter_n4); |
464 | salida_nivel(4) <= mux16(sel_auxn4, regn4(0 to 15)); |
465 | |
466 | ram_nivel20:RAMB16_S1 port map(DO => DO_n2(3 downto 3), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(3 downto 3), EN => EN_n2, SSR => SSR, WE => WE_n2(3)); |
467 | ram_nivel21:RAMB16_S1 port map(DO => DO_n2(2 downto 2), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(2 downto 2), EN => EN_n2, SSR => SSR, WE => WE_n2(2)); |
468 | ram_nivel22:RAMB16_S1 port map(DO => DO_n2(1 downto 1), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(1 downto 1), EN => EN_n2, SSR => SSR, WE => WE_n2(1)); |
469 | ram_nivel23:RAMB16_S1 port map(DO => DO_n2(0 downto 0), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(0 downto 0), EN => EN_n2, SSR => SSR, WE => WE_n2(0)); |
470 | |
471 | ram_nivel30:RAMB16_S1 port map(DO => DO_n3(3 downto 3), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(3 downto 3), EN => EN_n3, SSR => SSR, WE => WE_n3(3)); |
472 | ram_nivel31:RAMB16_S1 port map(DO => DO_n3(2 downto 2), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(2 downto 2), EN => EN_n3, SSR => SSR, WE => WE_n3(2)); |
473 | ram_nivel32:RAMB16_S1 port map(DO => DO_n3(1 downto 1), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(1 downto 1), EN => EN_n3, SSR => SSR, WE => WE_n3(1)); |
474 | ram_nivel33:RAMB16_S1 port map(DO => DO_n3(0 downto 0), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(0 downto 0), EN => EN_n3, SSR => SSR, WE => WE_n3(0)); |
475 | |
476 | ram_nivel40:RAMB16_S1 port map(DO => DO_n4(3 downto 3), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(3 downto 3), EN => EN_n4, SSR => SSR, WE => WE_n4(3)); |
477 | ram_nivel41:RAMB16_S1 port map(DO => DO_n4(2 downto 2), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(2 downto 2), EN => EN_n4, SSR => SSR, WE => WE_n4(2)); |
478 | ram_nivel42:RAMB16_S1 port map(DO => DO_n4(1 downto 1), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(1 downto 1), EN => EN_n4, SSR => SSR, WE => WE_n4(1)); |
479 | ram_nivel43:RAMB16_S1 port map(DO => DO_n4(0 downto 0), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(0 downto 0), EN => EN_n4, SSR => SSR, WE => WE_n4(0)); |
480 | |
481 | end Behavioral; |
482 | |
483 |
Branches:
master