Root/Examples/ADC/logic/ADC.v

1`timescale 1ns / 1ps
2module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
3                ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, irq_pin, OD1, OD2, OD3);
4  
5    parameter B = (7);
6
7    input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
8    inout [B:0] sram_data;
9    output led, ADC_CS, ADC_CSTART, ADC_SCLK;
10    output OD1, OD2, OD3;
11    inout ADC_SDIN, ADC_SDOUT;
12    input irq_pin;
13
14
15    // Internal conection
16    reg led;
17    reg OD1, OD2, OD3;
18
19    // synchronize signals
20    reg sncs, snwe;
21    reg [12:0] buffer_addr;
22    reg [B:0] buffer_data;
23
24    // bram interfaz signals
25    reg we;
26    reg w_st=0;
27    reg [B:0] wrBus;
28    wire [B:0] rdBus;
29    
30    // interfaz fpga signals
31    wire [12:0] addr;
32
33
34    reg [25:0] counter;
35 
36     // Test : LED blinking
37    always @(posedge clk) begin
38        if (~reset)
39            counter <= {25{1'b0}};
40        else
41            counter <= counter + 1;
42            led <= counter[25];
43            OD1 <= counter[25];
44            OD2 <= counter[16];
45            OD3 <= counter[15];
46
47    end
48    
49    // interefaz signals assignments
50    wire T = ~noe | ncs;
51    assign sram_data = T?8'bZ:rdBus;
52
53    // synchronize assignment
54    always @(negedge clk)
55    begin
56        sncs <= ncs;
57        snwe <= nwe;
58        buffer_data <= sram_data;
59        buffer_addr <= addr;
60    end
61
62    // write access cpu to bram
63    always @(posedge clk)
64    if(~reset) {w_st, we, wrBus} <= 0;
65      else begin
66        wrBus <= buffer_data;
67        case (w_st)
68          0: begin
69              we <= 0;
70              if(sncs | snwe) w_st <= 1;
71          end
72          1: begin
73            if(~(sncs | snwe)) begin
74              we <= 1;
75              w_st <= 0;
76            end
77            else we <= 0;
78          end
79        endcase
80      end
81
82    // Peripherals control
83    wire [3:0] csN;
84    wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
85      
86    assign csN = buffer_addr[12]? (buffer_addr[11]? 4'b1000:
87                                                    4'b0100)
88                                : (buffer_addr[11]? 4'b0010:
89                                                    4'b0001);
90
91    assign rdBus = buffer_addr[12]? (buffer_addr[11]? rdBus3:
92                                                      rdBus2)
93                                  : (buffer_addr[11]? rdBus1:
94                                                      rdBus0);
95                          
96    // Peripheral instantiation
97    ADC_peripheral P1(
98                        .clk(clk),
99                        .reset(~reset),
100                        .cs(csN[0]),
101                        .ADC_EOC(ADC_EOC),
102                        .ADC_CS(ADC_CS),
103                        .ADC_CSTART(ADC_CSTART),
104                        .ADC_SCLK(ADC_SCLK),
105                        .ADC_SDIN(ADC_SDIN),
106                        .ADC_SDOUT(ADC_SDOUT),
107                        .addr(buffer_addr[10:0]),
108                        .rdBus(rdBus0),
109                        .wrBus(wrBus),
110                        .we(we));
111endmodule
112
113

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