Root/Examples/ADC/logic/ADC_peripheral_tb.v

1`timescale 1ns / 1ps
2
3////////////////////////////////////////////////////////////////////////////////
4// Company:
5// Engineer:
6//
7// Create Date: 17:22:07 04/12/2010
8// Design Name: ADC_peripheral
9// Module Name: /home/juan64bits/ebd/ECB/nn-usb-fpga/Examples/ADC/logicISE/ADC_peripheral_tb.v
10// Project Name: logicISE
11// Target Device:
12// Tool versions:
13// Description:
14//
15// Verilog Test Fixture created by ISE for module: ADC_peripheral
16//
17// Dependencies:
18//
19// Revision:
20// Revision 0.01 - File Created
21// Additional Comments:
22//
23////////////////////////////////////////////////////////////////////////////////
24
25module ADC_peripheral_tb;
26
27    // Inputs
28    reg clk;
29    reg reset;
30    reg cs;
31    reg ADC_EOC;
32    reg [10:0] addr;
33    reg [7:0] wrBus;
34    reg we;
35
36    // Outputs
37    wire ADC_CS;
38    wire ADC_CSTART;
39    wire ADC_SCLK;
40    wire [7:0] rdBus;
41
42    // Bidirs
43    wire ADC_SDIN;
44    wire ADC_SDOUT;
45
46    // Instantiate the Unit Under Test (UUT)
47    ADC_peripheral uut (
48        .clk(clk),
49        .reset(reset),
50        .cs(cs),
51        .ADC_EOC(ADC_EOC),
52        .ADC_CS(ADC_CS),
53        .ADC_CSTART(ADC_CSTART),
54        .ADC_SCLK(ADC_SCLK),
55        .ADC_SDIN(ADC_SDIN),
56        .ADC_SDOUT(ADC_SDOUT),
57        .addr(addr),
58        .rdBus(rdBus),
59        .wrBus(wrBus),
60        .we(we)
61    );
62
63    initial begin
64        // Initialize Inputs
65        clk = 0;
66        reset = 0;
67        cs = 0;
68        ADC_EOC = 1;
69        addr = 0;
70        wrBus = 0;
71        we = 0;
72
73        // Wait 100 ns for global reset to finish
74        #100;
75        
76        addr = 0;
77        wrBus = 1;
78        we = 1;
79        cs = 1;
80        #20;
81        addr = 0;
82        wrBus = 0;
83        we = 0;
84        cs = 0;
85        #20;
86
87        addr = 1;
88        wrBus = 8;
89        we = 1;
90        cs = 1;
91        #20;
92        addr = 0;
93        wrBus = 0;
94        we = 0;
95        cs = 0;
96        #20;
97
98        addr = 2;
99        wrBus = 0;
100        we = 1;
101        cs = 1;
102        #20;
103        addr = 0;
104        wrBus = 0;
105        we = 0;
106        cs = 0;
107        #20;
108        
109        addr = 3;
110        wrBus = 0;
111        we = 1;
112        cs = 1;
113        #20;
114        addr = 3;
115        wrBus = 0;
116        we = 0;
117        cs = 0;
118        #20;
119        
120        addr = 3;
121        wrBus = 8'h39;
122        we = 1;
123        cs = 1;
124        #20;
125        addr = 3;
126        wrBus = 0;
127        we = 0;
128        cs = 1;
129        #20;
130
131    while(rdBus[5])
132    begin
133      #20;
134    end
135        #100;
136        addr = 3;
137        wrBus = 8'h39;
138        we = 1;
139        cs = 1;
140        #20;
141        addr = 3;
142        wrBus = 0;
143        we = 0;
144        cs = 1;
145        #20;
146
147    while(rdBus[5])
148    begin
149      #20;
150    end
151        #100;
152        addr = 0;
153        wrBus = 2;
154        we = 1;
155        cs = 1;
156        #20;
157        addr = 0;
158        wrBus = 0;
159        we = 0;
160        cs = 0;
161        #20;
162
163        addr = 1;
164        wrBus = 10;
165        we = 1;
166        cs = 1;
167        #20;
168        addr = 0;
169        wrBus = 0;
170        we = 0;
171        cs = 0;
172        #20;
173
174        addr = 2;
175        wrBus = 0;
176        we = 1;
177        cs = 1;
178        #20;
179        addr = 0;
180        wrBus = 0;
181        we = 0;
182        cs = 0;
183        #20;
184        
185        addr = 3;
186        wrBus = 8'h2B;
187        we = 1;
188        cs = 1;
189        #20;
190        addr = 3;
191        wrBus = 0;
192        we = 0;
193        cs = 1;
194        #20;
195
196    while(rdBus[5])
197    begin
198      #20;
199    end
200        #100;
201
202        addr = 1;
203        wrBus = 15;
204        we = 1;
205        cs = 1;
206        #20;
207        addr = 0;
208        wrBus = 0;
209        we = 0;
210        cs = 0;
211        #20;
212        
213        addr = 3;
214        wrBus = 8'h2C;
215        we = 1;
216        cs = 1;
217        #20;
218        addr = 3;
219        wrBus = 0;
220        we = 0;
221        cs = 1;
222        #20;
223
224    while(rdBus[5])
225    begin
226      #20;
227    end
228        #100;
229
230        addr = 1;
231        wrBus = 20;
232        we = 1;
233        cs = 1;
234        #20;
235        addr = 0;
236        wrBus = 0;
237        we = 0;
238        cs = 0;
239        #20;
240        
241        addr = 3;
242        wrBus = 8'h2D;
243        we = 1;
244        cs = 1;
245        #20;
246        addr = 3;
247        wrBus = 0;
248        we = 0;
249        cs = 1;
250        #20;
251
252    while(rdBus[5])
253    begin
254      #20;
255    end
256        #100;
257    end
258
259// Match Xport 2.0 50 MHz clock on FPGA (20ns period)
260always begin clk = ~clk; #10; end
261      
262endmodule
263
264

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