Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	module PIC ( DI, DO, addr,
2	ISRC_LP, nIRQ,
3	CS, nwe, noe,
4	MCLK,
5	RESET);
6
7	input [7:0] DI;
8	output [7:0] DO;
9	input [6:0] addr;
10	input [6:0] ISRC_LP;
11	output nIRQ;
12	input CS, nwe, noe;
13	input MCLK, RESET;
14
15	//------------------------------
16	// registros internos
17
18
19	reg nIRQ;
20
21	reg [7:0] DO; //Registro de salida.
22
23
24	reg [7:0] IRQEnable; //Interrupt Mask
25	reg IRQSoft; //Soft interrupt flag
26
27
28	wire [7:0] ISRCF, IREG_LP;
29
30	assign ISRCF = {ISRC_LP, IRQSoft}; //
31	assign IREG_LP = ( ISRCF & IRQEnable); //
32
33
34	always @(posedge MCLK)
35	begin
36	nIRQ <= ~(\|IREG_LP);
37	end
38
39
40	always @(CS or addr or noe or IREG_LP or ISRCF or IRQEnable)
41	begin
42	if (~CS & noe)
43	begin
44	case (addr)
45	7'b0000000: DO<=IREG_LP; //IRQStatus
46	7'b0000001: DO<=ISRCF; //IRQRawStatus
47	7'b0000010: DO<=IRQEnable; //IRQEnable
48	default: DO<=8'b0;
49	endcase
50	end
51	else DO<=8'b0;
52	end
53
54
55	always @(posedge MCLK or posedge RESET)
56	begin
57	if (RESET)
58	begin
59	IRQEnable <= 8'b0;
60	IRQSoft <= 1'b0;
61	end
62	else
63	begin
64	if (~CS & nwe)
65	begin
66	case (addr)
67	7'b0000010: IRQEnable <= ( DI \| IRQEnable); //EnableSet
68	7'b0000011: IRQEnable <= (~DI & IRQEnable); //EnableClear
69	7'b0000100: IRQSoft <= DI[1]; //Programmed IRQ
70	default: ;
71	endcase
72	end
73	end
74	end
75
76
77
78
79	endmodule
80

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