Hardware Design: SIE
Sign in or create your account | Project List | Help
Hardware Design: SIE Git Source Tree
Root/
1 | DESIGN = blink |
2 | PINS = $(DESIGN).ucf |
3 | DEVICE = xc3s500e-VQ100-4 |
4 | BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ |
5 | -g CRC:enable -g StartUpClk:CCLK |
6 | |
7 | SIM_CMD = vsim |
8 | SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do |
9 | SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) |
10 | IVERILOG = iverilog |
11 | |
12 | SAKC_IP = 192.168.254.101 |
13 | |
14 | SRC = $(DESIGN).v |
15 | |
16 | SIM_SRC = $(DESIGN)_TB.v \ |
17 | sim/unisims/BUFG.v \ |
18 | sim/unisims/DCM.v \ |
19 | sim/unisims/FDDRRSE.v |
20 | |
21 | |
22 | |
23 | all: bits |
24 | |
25 | remake: clean-build all |
26 | |
27 | clean: |
28 | rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat |
29 | rm -f *.bit |
30 | |
31 | cleanall: clean |
32 | rm -rf build simulation/work simulation/transcript simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd |
33 | |
34 | bits: $(DESIGN).bit |
35 | |
36 | # |
37 | # Synthesis |
38 | # |
39 | build/project.src: |
40 | @[ -d build ] || mkdir build |
41 | @rm -f $@ |
42 | for i in $(SRC); do echo verilog work ../$$i >> $@; done |
43 | for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done |
44 | |
45 | build/project.xst: build/project.src |
46 | echo "run" > $@ |
47 | echo "-top $(DESIGN) " >> $@ |
48 | echo "-p $(DEVICE)" >> $@ |
49 | echo "-opt_mode Area" >> $@ |
50 | echo "-opt_level 1" >> $@ |
51 | echo "-ifn project.src" >> $@ |
52 | echo "-ifmt mixed" >> $@ |
53 | echo "-ofn project.ngc" >> $@ |
54 | echo "-ofmt NGC" >> $@ |
55 | echo "-rtlview yes" >> $@ |
56 | |
57 | build/project.ngc: build/project.xst $(SRC) |
58 | cd build && xst -ifn project.xst -ofn project.log |
59 | |
60 | build/project.ngd: build/project.ngc $(PINS) |
61 | cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS) |
62 | |
63 | build/project.ncd: build/project.ngd |
64 | cd build && map -pr b -p $(DEVICE) project |
65 | |
66 | build/project_r.ncd: build/project.ncd |
67 | cd build && par -w project project_r.ncd |
68 | |
69 | build/project_r.twr: build/project_r.ncd |
70 | cd build && trce -v 25 project_r.ncd project.pcf |
71 | |
72 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr |
73 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) |
74 | @mv -f build/project_r.bit $@ |
75 | |
76 | build/project_r.v: build/project_r.ncd |
77 | cd build && ngd2ver project.ngd -w project.v |
78 | |
79 | modelsim: |
80 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
81 | |
82 | timesim: build/project_r.v |
83 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do |
84 | |
85 | iversim: |
86 | $(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB |
87 | vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/ |
88 | gtkwave simulation/$(DESIGN)_TB.vcd& |
89 | |
90 | upload: $(DESIGN).bit |
91 | scp $(DESIGN).bit root@$(SAKC_IP): |
92 |
Branches:
master