Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2
3	module blink_TB;
4
5	reg clk;
6	reg reset;
7	wire led;
8
9	blink uut ( .clk(clk), .reset(reset), .led(led));
10
11	parameter PERIOD = 20;
12	parameter real DUTY_CYCLE = 0.5;
13	parameter OFFSET = 0;
14	parameter TSET = 3;
15	parameter THLD = 3;
16	parameter NWS = 3;
17
18	event reset_trigger;
19
20
21	initial begin // Initialize Inputs
22	clk = 0; reset = 0;
23	end
24
25	initial begin // Process for clk
26	#OFFSET;
27	forever
28	begin
29	clk = 1'b0;
30	#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
31	#(PERIOD*DUTY_CYCLE);
32	end
33	end
34
35	initial begin // Reset the system, Start the image capture process
36	forever begin
37	@ (reset_trigger);
38	@ (negedge clk);
39	reset = 1;
40	@ (negedge clk);
41	reset = 0;
42	end
43	end
44
45
46	initial begin: TEST_CASE
47	$dumpfile("blink_TB.vcd");
48	$dumpvars(-1, uut);
49
50	#10 -> reset_trigger;
51	#((PERIODDUTY_CYCLE)100) $finish;
52	end
53
54	endmodule
55
56

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