Hardware Design: SIE
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| 1 | ------------------------------------------------------------------------------- |
| 2 | -- -- |
| 3 | -- MT32 - Mersenne Twister -- |
| 4 | -- Copyright (C) 2007 HT-LAB -- |
| 5 | -- -- |
| 6 | -- Contact : Use feedback form on the website. -- |
| 7 | -- Web: http://www.ht-lab.com -- |
| 8 | -- -- |
| 9 | -- MT32 files are released under the GNU General Public License. -- |
| 10 | -- -- |
| 11 | ------------------------------------------------------------------------------- |
| 12 | -- -- |
| 13 | -- This library is free software; you can redistribute it and/or -- |
| 14 | -- modify it under the terms of the GNU Lesser General Public -- |
| 15 | -- License as published by the Free Software Foundation; either -- |
| 16 | -- version 2.1 of the License, or (at your option) any later version. -- |
| 17 | -- -- |
| 18 | -- This library is distributed in the hope that it will be useful, -- |
| 19 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
| 20 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- |
| 21 | -- Lesser General Public License for more details. -- |
| 22 | -- -- |
| 23 | -- Full details of the license can be found in the file "copying.txt". -- |
| 24 | -- -- |
| 25 | -- You should have received a copy of the GNU Lesser General Public -- |
| 26 | -- License along with this library; if not, write to the Free Software -- |
| 27 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
| 28 | -- -- |
| 29 | ------------------------------------------------------------------------------- |
| 30 | -- -- |
| 31 | -- Counters, instantiated in top level -- |
| 32 | ------------------------------------------------------------------------------- |
| 33 | LIBRARY ieee; |
| 34 | USE ieee.std_logic_1164.all; |
| 35 | USE ieee.std_logic_arith.all; |
| 36 | USE ieee.std_logic_unsigned.all; |
| 37 | |
| 38 | ENTITY counters IS |
| 39 | GENERIC( |
| 40 | M : integer := 397; |
| 41 | N : integer := 623 |
| 42 | ); |
| 43 | PORT( |
| 44 | clk : IN std_logic; |
| 45 | resetn : IN std_logic; |
| 46 | ena : IN std_logic; |
| 47 | wea : OUT std_logic; |
| 48 | kk_cnt : OUT std_logic_vector (9 DOWNTO 0); |
| 49 | km_cnt : OUT std_logic_vector (9 DOWNTO 0); |
| 50 | kp_cnt : OUT std_logic_vector (9 DOWNTO 0); |
| 51 | wr_cnt : OUT std_logic_vector (9 DOWNTO 0) |
| 52 | ); |
| 53 | |
| 54 | END counters ; |
| 55 | |
| 56 | -- |
| 57 | ARCHITECTURE rtl OF counters IS |
| 58 | |
| 59 | signal kk_cnt_s : std_logic_vector (9 DOWNTO 0); |
| 60 | signal km_cnt_s : std_logic_vector (9 DOWNTO 0); |
| 61 | signal kp_cnt_s : std_logic_vector (9 DOWNTO 0); |
| 62 | |
| 63 | signal wr_cnt_s : std_logic_vector (9 DOWNTO 0); |
| 64 | |
| 65 | BEGIN |
| 66 | |
| 67 | process (clk,resetn) |
| 68 | begin |
| 69 | if (resetn='0') then |
| 70 | wea <= '0'; |
| 71 | elsif (rising_edge(clk)) then |
| 72 | wea <= ena; -- wea is delayed by 1 clock cycle to |
| 73 | end if; -- prevent writing outside the dpram address |
| 74 | end process; -- address range (0..623) |
| 75 | |
| 76 | |
| 77 | ------------------------------------------------------------------------------- |
| 78 | -- Write counter which is equal to kk-1 |
| 79 | -- Required to achieve single cycle read/write |
| 80 | ------------------------------------------------------------------------------- |
| 81 | process (clk,resetn) |
| 82 | begin |
| 83 | if (resetn='0') then |
| 84 | wr_cnt_s <= (others => '1'); |
| 85 | elsif (rising_edge(clk)) then |
| 86 | if (wr_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then |
| 87 | wr_cnt_s <= (others => '0'); |
| 88 | elsif ena='1' then |
| 89 | wr_cnt_s <= wr_cnt_s + '1'; |
| 90 | end if; |
| 91 | end if; |
| 92 | end process; |
| 93 | wr_cnt <= wr_cnt_s; |
| 94 | |
| 95 | |
| 96 | ------------------------------------------------------------------------------- |
| 97 | -- kk Counter |
| 98 | ------------------------------------------------------------------------------- |
| 99 | process (clk,resetn) |
| 100 | begin |
| 101 | if (resetn='0') then |
| 102 | kk_cnt_s <= (others => '0'); |
| 103 | elsif (rising_edge(clk)) then |
| 104 | if (kk_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then |
| 105 | kk_cnt_s <= (others => '0'); |
| 106 | elsif ena='1' then |
| 107 | kk_cnt_s <= kk_cnt_s + '1'; |
| 108 | end if; |
| 109 | end if; |
| 110 | end process; |
| 111 | kk_cnt <= kk_cnt_s; |
| 112 | |
| 113 | ------------------------------------------------------------------------------- |
| 114 | -- kp Counter |
| 115 | ------------------------------------------------------------------------------- |
| 116 | process (clk,resetn) |
| 117 | begin |
| 118 | if (resetn='0') then |
| 119 | kp_cnt_s <= "0000000001"; |
| 120 | elsif (rising_edge(clk)) then |
| 121 | if (kp_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then |
| 122 | kp_cnt_s <= (others => '0'); |
| 123 | elsif ena='1' then |
| 124 | kp_cnt_s <= kp_cnt_s + '1'; |
| 125 | end if; |
| 126 | end if; |
| 127 | end process; |
| 128 | kp_cnt <= kp_cnt_s; |
| 129 | |
| 130 | ------------------------------------------------------------------------------- |
| 131 | -- km Counter |
| 132 | ------------------------------------------------------------------------------- |
| 133 | process (clk,resetn) |
| 134 | begin |
| 135 | if (resetn='0') then |
| 136 | km_cnt_s <= CONV_STD_LOGIC_VECTOR(M,10); |
| 137 | elsif (rising_edge(clk)) then |
| 138 | if (km_cnt_s = CONV_STD_LOGIC_VECTOR(N,10)) then |
| 139 | km_cnt_s <= (others => '0'); |
| 140 | elsif ena='1' then |
| 141 | km_cnt_s <= km_cnt_s + '1'; |
| 142 | end if; |
| 143 | end if; |
| 144 | end process; |
| 145 | km_cnt <= km_cnt_s; |
| 146 | |
| 147 | end architecture rtl; |
| 148 |
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