Root/Examples/ehw4/logic/evalfit_peripheral.vhd

1-- 07/11/08
2-- Evalfit_peripheral
3-- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables ***
4-- Funciona hasta con 14 vars.
5-- mapa:
6    -- 0 - 0x3F Cromosoma (cada uno con 64-bit)
7    -- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB.
8    
9
10-- Mapa de cromosoma:
11    -- bit bit Contenido
12    -- 28 a 31 Nivel del arbol
13    -- 32 a 47 LUT o tabla del arbol LUT(32)MSB, LUT(47)LSB,
14    -- 48 a 63 Variables de entrada del arbol (4 bits por variable) 48-51 MSB, 60-63 LSB
15
16library IEEE;
17use IEEE.STD_LOGIC_1164.ALL;
18use IEEE.STD_LOGIC_ARITH.ALL;
19use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating
20---- any Xilinx primitives in this code.
21library UNISIM;
22use UNISIM.VComponents.all;
23
24entity evalfit_peripheral is
25    Port ( clk, reset, habilita: in STD_LOGIC;
26            maxcombs : in STD_LOGIC_VECTOR (0 to 15);
27              nivel_max : in STD_LOGIC_VECTOR (0 to 3);
28         peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
29            peripheral_mem_en : out std_logic;
30         peripheral_mem_out: out STD_LOGIC_VECTOR (0 to 63);
31            peripheral_mem_we : out STD_LOGIC;
32            peripheral_mem_addr: out STD_LOGIC_VECTOR (0 to 8);
33            evalfit3_estado : out std_logic_vector(0 to 15);
34            errores : out STD_LOGIC_VECTOR (0 to 15);
35            fin_ack : out std_logic;
36            reg0_s : out STD_LOGIC_VECTOR (0 to 31);
37            reg1_s : out STD_LOGIC_VECTOR (0 to 31);
38            reg2_s : out STD_LOGIC_VECTOR (0 to 31);
39            reg3_s : out STD_LOGIC_VECTOR (0 to 31);
40            reg4_s : out STD_LOGIC_VECTOR (0 to 31)
41            );
42end evalfit_peripheral;
43
44architecture Behavioral of evalfit_peripheral is
45
46function mux16(sel: in std_logic_vector(0 to 3); ent: in std_logic_vector(0 to 15)) return std_logic is
47begin
48  case sel is
49    when "0000" => return ent(15);
50    when "0001" => return ent(14);
51    when "0010" => return ent(13);
52    when "0011" => return ent(12);
53    when "0100" => return ent(11);
54    when "0101" => return ent(10);
55    when "0110" => return ent(9);
56    when "0111" => return ent(8);
57     when "1000" => return ent(7);
58    when "1001" => return ent(6);
59    when "1010" => return ent(5);
60    when "1011" => return ent(4);
61    when "1100" => return ent(3);
62    when "1101" => return ent(2);
63    when "1110" => return ent(1);
64    when others => return ent(0);
65  end case;
66end mux16;
67
68function mux4(sel: in std_logic_vector(0 to 1); ent: in std_logic_vector(0 to 3)) return std_logic is
69begin
70  case sel is
71    when "00" => return ent(3);
72    when "01" => return ent(2);
73    when "10" => return ent(1);
74    when others => return ent(0);
75  end case;
76end mux4;
77
78-- senales para evaluar funciones
79signal reg0, reg1, reg2, reg3, reg4, regn3, regn4:STD_LOGIC_VECTOR (0 to 31);
80signal reg0_sig, reg1_sig, reg2_sig, reg3_sig, reg4_sig, regn3_sig, regn4_sig :STD_LOGIC_VECTOR (0 to 31);
81signal sel_aux0, sel_aux1, sel_aux2, sel_aux3, sel_aux4, sel_auxn3, sel_auxn4, sal_arbol, minter_n3, minter_n4 : std_logic_vector(0 to 3);
82signal salida_s, fin_ack_sig, fifow_wrreq_sig: std_logic;
83signal entrada, errores_aux, errores_sig, salida_nivel : STD_LOGIC_VECTOR (0 to 15);
84
85-- senales para las memorias, guardan resultados de arboles intermedios
86signal DO_n2, DI_n2, DO_n3, DI_n3, DO_n4, DI_n4: std_logic_vector(3 downto 0);
87signal ADDR_n2, ADDR_n3, ADDR_n4: std_logic_vector(0 to 13);
88signal WE_n2, WE_n3, WE_n4: std_logic_vector(3 downto 0);
89signal WE_n2_sig, WE_n3_sig, WE_n4_sig: std_logic_vector(3 downto 0);
90signal EN_n2, SSR, EN_n3, EN_n4: std_logic;
91
92-- senales para el control
93type estado is (reset1, reset2, inicio, proceso, n1, n2, n3, n4, precuenta, cuenta, final, final2);
94signal ep, es: estado;
95signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3);
96signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1);
97signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15);
98signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 15);
99signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8);
100
101begin
102
103
104process(ep, habilita, reg0, reg1, reg2, reg3, reg4, regn3, regn4, nivel, c1, c2, c3, c4, conta,
105        salida_s, salida_nivel, WE_n2, WE_n3, WE_n4, nivel_max,
106        maxcombs, peripheral_mem_in, peripheral_mem_addr_crom, peripheral_mem_addr_aux)
107begin
108es <= reset1;
109WE_n2_sig <= "0000";
110WE_n3_sig <= "0000";
111WE_n4_sig <= "0000";
112reg0_sig <= reg0;
113reg1_sig <= reg1;
114reg2_sig <= reg2;
115reg3_sig <= reg3;
116reg4_sig <= reg4;
117regn3_sig <= regn3;
118regn4_sig <= regn4;
119conta_sig <= conta;
120conta2_sig <= conta2;
121c1_sig <= c1;
122c2_sig <= c2;
123c3_sig <= c3;
124c4_sig <= c4;
125DI_n2 <= "0000";
126DI_n3 <= "0000";
127DI_n4 <= "0000";
128fin_ack_sig <= '0';
129peripheral_mem_addr_sig <= peripheral_mem_addr_aux;
130peripheral_mem_addr_crom_sig <= peripheral_mem_addr_crom;
131peripheral_mem_we <= '0';
132peripheral_mem_en <= '0';
133errores_sig <= errores_aux;
134nivel_sig <= nivel_reg;
135estado_evalf3_sig <= x"FFFF";
136case ep is
137    when reset1 => --poner la memoria a 0000
138            WE_n2_sig <= "1111";
139            WE_n3_sig <= "1111";
140            WE_n4_sig <= "1111";
141            conta2_sig <= (others => '0');
142            estado_evalf3_sig <= x"0001";
143            es <= reset2;
144    when reset2 =>
145            DI_n2 <= "0000";
146            DI_n3 <= "0000";
147            DI_n4 <= "0000";
148            estado_evalf3_sig <= x"0002";
149            if(conta2 = maxcombs)then
150                WE_n2_sig <= "0000";
151                WE_n3_sig <= "0000";
152                WE_n4_sig <= "0000";
153                conta2_sig <= (others => '0');
154                es <= inicio;
155            else
156                WE_n2_sig <= "1111";
157                WE_n3_sig <= "1111";
158                WE_n4_sig <= "1111";
159                conta2_sig <= conta2 + 1;
160                es <= reset2;
161            end if;
162            
163    when inicio =>
164            if(habilita = '0') then
165                es <= inicio;
166                conta_sig <= (others => '0');
167                conta2_sig <= (others => '0');
168                peripheral_mem_addr_sig <= (others => '0');
169                c1_sig <= "00";
170                c2_sig <= "00";
171                c3_sig <= "00";
172                c4_sig <= "00";
173                errores_sig <= x"0000";
174            else
175                es <= proceso;
176                peripheral_mem_en <= '1';
177            end if;
178            estado_evalf3_sig <= x"0003";
179
180    when proceso =>
181            peripheral_mem_en <= '1';
182            if(nivel = "0001")then
183                case c1 is
184                    when "00" => reg0_sig <= peripheral_mem_in(32 to 63);
185                    when "01" => reg1_sig <= peripheral_mem_in(32 to 63);
186                    when "10" => reg2_sig <= peripheral_mem_in(32 to 63);
187                    when others => reg3_sig <= peripheral_mem_in(32 to 63);
188                end case;
189                es <= n1;
190            elsif(nivel = "0010")then
191                reg4_sig <= peripheral_mem_in(32 to 63);
192                WE_n2_sig(conv_integer(c2)) <= '1';
193                DI_n2(conv_integer(c2)) <= salida_nivel(2);
194                es <= n2;
195            elsif(nivel = "0011")then
196                regn3_sig <= peripheral_mem_in(32 to 63);
197                WE_n3_sig(conv_integer(c3)) <= '1';
198                DI_n3(conv_integer(c3)) <= salida_nivel(3);
199                es <= n3;
200            elsif(nivel = "0100")then
201                regn4_sig <= peripheral_mem_in(32 to 63);
202                WE_n4_sig(conv_integer(c4)) <= '1';
203                DI_n4(conv_integer(c4)) <= salida_nivel(4);
204                es <= n4;
205            elsif(nivel = "1111")then
206                es <= final2;
207            end if;
208            peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1;
209            peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1;
210            nivel_sig <= nivel;
211            estado_evalf3_sig <= peripheral_mem_in(48 to 63);--x"FFE" & nivel;----x"02";
212
213    when n1 =>
214            peripheral_mem_en <= '1';
215            c1_sig <= c1 + 1;
216            peripheral_mem_addr_sig <= peripheral_mem_addr_aux;
217            es <= proceso;
218            estado_evalf3_sig <= x"0004";
219
220    when n2 =>
221            WE_n2_sig(conv_integer(c2)) <= '1';
222            DI_n2(conv_integer(c2)) <= salida_nivel(2);
223            peripheral_mem_en <= '1';
224            peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida
225            es <= precuenta;
226            conta2_sig <= (others => '0');
227            estado_evalf3_sig <= x"0005";
228
229    when n3 =>
230            WE_n3_sig(conv_integer(c3)) <= '1';
231            DI_n3(conv_integer(c3)) <= salida_nivel(3);
232            peripheral_mem_en <= '1';
233            peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
234            es <= precuenta;
235            conta2_sig <= (others => '0');
236            estado_evalf3_sig <= x"0006";
237
238    when n4 =>
239            WE_n4_sig(conv_integer(c4)) <= '1';
240            DI_n4(conv_integer(c4)) <= salida_nivel(4);
241            peripheral_mem_en <= '1';
242            peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
243            es <= precuenta;
244            conta2_sig <= (others => '0');
245            estado_evalf3_sig <= x"0007";
246
247    when precuenta =>
248            WE_n2_sig <= WE_n2;
249            WE_n3_sig <= WE_n3;
250            WE_n4_sig <= WE_n4;
251            DI_n2(conv_integer(c2)) <= salida_nivel(2);
252            DI_n3(conv_integer(c3)) <= salida_nivel(3);
253            DI_n4(conv_integer(c4)) <= salida_nivel(4);
254            peripheral_mem_en <= '1';
255            peripheral_mem_addr_sig <= "001000000" + ('0' & conta2(2 to 9));
256            conta_sig <= conta;
257            conta2_sig <= conta + 1;
258            es <= cuenta;
259            estado_evalf3_sig <= x"0008";
260
261    when cuenta =>
262            DI_n2(conv_integer(c2)) <= salida_nivel(2);
263            DI_n3(conv_integer(c3)) <= salida_nivel(3);
264            DI_n4(conv_integer(c4)) <= salida_nivel(4);
265            peripheral_mem_en <= '1';
266            if(conta = maxcombs)then
267                WE_n2_sig <= "0000";
268                WE_n3_sig <= "0000";
269                WE_n4_sig <= "0000";
270                conta_sig <= (others => '0');
271                conta2_sig <= (others => '0');
272                peripheral_mem_addr_sig <= peripheral_mem_addr_crom; --direccion de mem donde esta el cromosoma
273                es <= final;
274            else
275                WE_n2_sig <= WE_n2;
276                WE_n3_sig <= WE_n3;
277                WE_n4_sig <= WE_n4;
278                conta_sig <= conta + 1;
279                conta2_sig <= conta2 + 1;
280                peripheral_mem_addr_sig <= "001000000" + ('0' & conta2(2 to 9));--crear señal conta futura
281                if(conta(10 to 15) = "111111")then
282                    es <= precuenta;
283                else
284                    es <= cuenta;
285                end if;
286            end if;
287            if(nivel_reg = nivel_max)then
288                if(salida_nivel(conv_integer(nivel_max)) = peripheral_mem_in(conv_integer(conta(10 to 15))))then
289                    errores_sig <= errores_aux;
290                else
291                    errores_sig <= errores_aux + 1;
292                end if;
293            else
294                errores_sig <= errores_aux;
295            end if;
296            
297            estado_evalf3_sig <= x"0009";
298                
299    when final =>
300             if(nivel_reg = "0010")then
301                c2_sig <= c2 + 1;
302            elsif(nivel_reg = "0011")then
303                c3_sig <= c3 + 1;
304            elsif(nivel_reg = "0100")then
305                c4_sig <= c4 + 1;
306            end if;
307            peripheral_mem_en <= '1';
308            peripheral_mem_addr_sig <= peripheral_mem_addr_crom;
309            es <= proceso;
310            estado_evalf3_sig <= x"000A";
311            
312    when final2 =>
313            if(habilita = '1') then
314                es <= final2;
315            else
316                es <= inicio;
317            end if;
318            fin_ack_sig <= '1';
319            estado_evalf3_sig <= x"000B";
320    when others => es <= inicio;
321
322    end case;
323end process;
324
325
326process(clk, reset)
327begin
328    if(reset = '1')then
329        ep <= reset1;
330        c1 <= "00";
331        c2 <= "00";
332        c3 <= "00";
333        c4 <= "00";
334        WE_n2 <= "0000";
335        WE_n3 <= "0000";
336        WE_n4 <= "0000";
337        reg0 <= x"00000000";
338        reg1 <= x"00000000";
339        reg2 <= x"00000000";
340        reg3 <= x"00000000";
341        reg4 <= x"00000000";
342        regn3 <= x"00000000";
343        regn4 <= x"00000000";
344        conta <= (others => '0');
345        conta2 <= (others => '0');
346        fin_ack <= '0';
347        peripheral_mem_addr_aux <= "000000000";
348         peripheral_mem_addr_crom <= "000000000";
349        errores_aux <= (others => '0');
350        nivel_reg <= "0000";
351        estado_evalf3 <= x"0000";
352    elsif(rising_edge(clk))then
353        ep <= es;
354        c1 <= c1_sig;
355        c2 <= c2_sig;
356        c3 <= c3_sig;
357        c4 <= c4_sig;
358        WE_n2 <= WE_n2_sig;
359        WE_n3 <= WE_n3_sig;
360        WE_n4 <= WE_n4_sig;
361        reg0 <= reg0_sig;
362        reg1 <= reg1_sig;
363        reg2 <= reg2_sig;
364        reg3 <= reg3_sig;
365        reg4 <= reg4_sig;
366        regn3 <= regn3_sig;
367        regn4 <= regn4_sig;
368        conta <= conta_sig;
369        conta2 <= conta2_sig;
370        fin_ack <= fin_ack_sig;
371        peripheral_mem_addr_aux <= peripheral_mem_addr_sig;
372        peripheral_mem_addr_crom <= peripheral_mem_addr_crom_sig;
373        errores_aux <= errores_sig;
374        nivel_reg <= nivel_sig;
375        estado_evalf3 <= estado_evalf3_sig;
376    end if;
377end process;
378
379process(nivel_reg, conta, conta2)
380begin
381case nivel_reg is
382    when "0000" =>
383        ADDR_n2 <= conta(2 to 15);
384        ADDR_n3 <= conta(2 to 15);
385        ADDR_n4 <= conta(2 to 15);
386    when "0010" =>
387        ADDR_n2 <= conta(2 to 15);
388        ADDR_n3 <= conta(2 to 15);
389        ADDR_n4 <= conta(2 to 15);
390    when "0011" =>
391        ADDR_n2 <= conta2(2 to 15);
392        ADDR_n3 <= conta(2 to 15);
393        ADDR_n4 <= conta(2 to 15);
394    when "0100" =>
395        ADDR_n2 <= conta(2 to 15);
396        ADDR_n3 <= conta2(2 to 15);
397        ADDR_n4 <= conta(2 to 15);
398    when others =>
399        ADDR_n2 <= conta2(2 to 15);
400        ADDR_n3 <= conta2(2 to 15);
401        ADDR_n4 <= conta2(2 to 15);
402end case;
403
404end process;
405
406
407errores <= errores_aux;
408peripheral_mem_addr <= peripheral_mem_addr_aux;
409nivel <= peripheral_mem_in(28 to 31);
410EN_n2 <= '1';
411EN_n3 <= '1';
412EN_n4 <= '1';
413SSR <= '0';
414minter_n3 <= DO_n2;
415minter_n4 <= DO_n3;
416entrada <= conta;
417
418evalfit3_estado <= estado_evalf3;
419reg0_s <= reg0;
420reg1_s <= reg1;
421reg2_s <= reg2;
422reg3_s <= reg3;
423reg4_s <= reg4;
424salida_nivel(1) <= sal_arbol(3);
425
426sel_aux0(3) <= mux16(reg0(28 to 31), entrada);
427sel_aux0(2) <= mux16(reg0(24 to 27), entrada);
428sel_aux0(1) <= mux16(reg0(20 to 23), entrada);
429sel_aux0(0) <= mux16(reg0(16 to 19), entrada);
430sal_arbol(3) <= mux16(sel_aux0, reg0(0 to 15)); -- reg0(0 to 15) = dato_lut
431
432sel_aux1(3) <= mux16(reg1(28 to 31), entrada);
433sel_aux1(2) <= mux16(reg1(24 to 27), entrada);
434sel_aux1(1) <= mux16(reg1(20 to 23), entrada);
435sel_aux1(0) <= mux16(reg1(16 to 19), entrada);
436sal_arbol(2) <= mux16(sel_aux1, reg1(0 to 15));
437
438sel_aux2(3) <= mux16(reg2(28 to 31), entrada);
439sel_aux2(2) <= mux16(reg2(24 to 27), entrada);
440sel_aux2(1) <= mux16(reg2(20 to 23), entrada);
441sel_aux2(0) <= mux16(reg2(16 to 19), entrada);
442sal_arbol(1) <= mux16(sel_aux2, reg2(0 to 15));
443
444sel_aux3(3) <= mux16(reg3(28 to 31), entrada);
445sel_aux3(2) <= mux16(reg3(24 to 27), entrada);
446sel_aux3(1) <= mux16(reg3(20 to 23), entrada);
447sel_aux3(0) <= mux16(reg3(16 to 19), entrada);
448sal_arbol(0) <= mux16(sel_aux3, reg3(0 to 15));
449
450sel_aux4(3) <= mux4(reg4(30 to 31), sal_arbol); --arbol de 2do nivel
451sel_aux4(2) <= mux4(reg4(26 to 27), sal_arbol);
452sel_aux4(1) <= mux4(reg4(22 to 23), sal_arbol);
453sel_aux4(0) <= mux4(reg4(18 to 19), sal_arbol);
454salida_nivel(2) <= mux16(sel_aux4, reg4(0 to 15));
455
456sel_auxn3(3) <= mux4(regn3(30 to 31), minter_n3); --arboles de 3er nivel
457sel_auxn3(2) <= mux4(regn3(26 to 27), minter_n3);
458sel_auxn3(1) <= mux4(regn3(22 to 23), minter_n3);
459sel_auxn3(0) <= mux4(regn3(18 to 19), minter_n3);
460salida_nivel(3) <= mux16(sel_auxn3, regn3(0 to 15));
461
462sel_auxn4(3) <= mux4(regn4(30 to 31), minter_n4); --arboles de 4to nivel
463sel_auxn4(2) <= mux4(regn4(26 to 27), minter_n4);
464sel_auxn4(1) <= mux4(regn4(22 to 23), minter_n4);
465sel_auxn4(0) <= mux4(regn4(18 to 19), minter_n4);
466salida_nivel(4) <= mux16(sel_auxn4, regn4(0 to 15));
467
468ram_nivel20:RAMB16_S1 port map(DO => DO_n2(3 downto 3), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(3 downto 3), EN => EN_n2, SSR => SSR, WE => WE_n2(3));
469ram_nivel21:RAMB16_S1 port map(DO => DO_n2(2 downto 2), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(2 downto 2), EN => EN_n2, SSR => SSR, WE => WE_n2(2));
470ram_nivel22:RAMB16_S1 port map(DO => DO_n2(1 downto 1), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(1 downto 1), EN => EN_n2, SSR => SSR, WE => WE_n2(1));
471ram_nivel23:RAMB16_S1 port map(DO => DO_n2(0 downto 0), ADDR => ADDR_n2, CLK => clk, DI => DI_n2(0 downto 0), EN => EN_n2, SSR => SSR, WE => WE_n2(0));
472
473ram_nivel30:RAMB16_S1 port map(DO => DO_n3(3 downto 3), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(3 downto 3), EN => EN_n3, SSR => SSR, WE => WE_n3(3));
474ram_nivel31:RAMB16_S1 port map(DO => DO_n3(2 downto 2), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(2 downto 2), EN => EN_n3, SSR => SSR, WE => WE_n3(2));
475ram_nivel32:RAMB16_S1 port map(DO => DO_n3(1 downto 1), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(1 downto 1), EN => EN_n3, SSR => SSR, WE => WE_n3(1));
476ram_nivel33:RAMB16_S1 port map(DO => DO_n3(0 downto 0), ADDR => ADDR_n3, CLK => clk, DI => DI_n3(0 downto 0), EN => EN_n3, SSR => SSR, WE => WE_n3(0));
477
478ram_nivel40:RAMB16_S1 port map(DO => DO_n4(3 downto 3), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(3 downto 3), EN => EN_n4, SSR => SSR, WE => WE_n4(3));
479ram_nivel41:RAMB16_S1 port map(DO => DO_n4(2 downto 2), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(2 downto 2), EN => EN_n4, SSR => SSR, WE => WE_n4(2));
480ram_nivel42:RAMB16_S1 port map(DO => DO_n4(1 downto 1), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(1 downto 1), EN => EN_n4, SSR => SSR, WE => WE_n4(1));
481ram_nivel43:RAMB16_S1 port map(DO => DO_n4(0 downto 0), ADDR => ADDR_n4, CLK => clk, DI => DI_n4(0 downto 0), EN => EN_n4, SSR => SSR, WE => WE_n4(0));
482
483end Behavioral;
484
485

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