Root/Examples/ehw4/logic/mt.vhd

1-------------------------------------------------------------------------------
2-- --
3-- MT32 - Mersenne Twister --
4-- Copyright (C) 2007 HT-LAB --
5-- --
6-- Contact : Use feedback form on the website. --
7-- Web: http://www.ht-lab.com --
8-- --
9-- MT32 files are released under the GNU General Public License. --
10-- --
11-------------------------------------------------------------------------------
12-- --
13-- This library is free software; you can redistribute it and/or --
14-- modify it under the terms of the GNU Lesser General Public --
15-- License as published by the Free Software Foundation; either --
16-- version 2.1 of the License, or (at your option) any later version. --
17-- --
18-- This library is distributed in the hope that it will be useful, --
19-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
20-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
21-- Lesser General Public License for more details. --
22-- --
23-- Full details of the license can be found in the file "copying.txt". --
24-- --
25-- You should have received a copy of the GNU Lesser General Public --
26-- License along with this library; if not, write to the Free Software --
27-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
28-- --
29-------------------------------------------------------------------------------
30-- --
31-- Top Level (Synthesis) --
32-------------------------------------------------------------------------------
33LIBRARY ieee;
34USE ieee.std_logic_1164.all;
35USE ieee.std_logic_unsigned.all;
36USE ieee.std_logic_arith.all;
37
38ENTITY mt_mem IS
39   PORT(
40      clk : IN std_logic;
41      ena : IN std_logic;
42      resetn : IN std_logic;
43      random : OUT std_logic_vector (31 DOWNTO 0)
44   );
45
46END mt_mem ;
47
48LIBRARY ieee;
49
50ARCHITECTURE struct OF mt_mem IS
51
52   -- Architecture declarations
53
54   -- internal signal declarations
55    signal kk_cnt : std_logic_vector(9 downto 0);
56    signal km_cnt : std_logic_vector(9 downto 0);
57    signal kp_cnt : std_logic_vector(9 downto 0);
58    signal mt_kk31 : std_logic_vector(0 downto 0);
59    signal mt_kk_s : std_logic_vector(31 downto 0);
60    signal mt_km : std_logic_vector(31 downto 0);
61    signal mt_kp : std_logic_vector(30 downto 0);
62    signal wea : std_logic;
63    signal wea_s : std_logic_vector(0 downto 0);
64    signal wr_cnt : std_logic_vector(9 downto 0);
65
66
67    signal xor1_s : std_logic_vector(31 downto 0);
68    signal xor2_s : std_logic_vector(31 downto 0);
69    signal xor3_s : std_logic_vector(31 downto 0);
70    signal y_s : std_logic_vector(31 downto 0);
71    signal mag01_s : std_logic_vector(31 downto 0);
72
73   -- Component Declarations
74   COMPONENT counters
75   GENERIC (
76      M : integer := 397;
77      N : integer := 623
78   );
79   PORT (
80      clk : IN std_logic ;
81      resetn : IN std_logic ;
82      ena : IN std_logic ;
83      wea : OUT std_logic ;
84      kk_cnt : OUT std_logic_vector (9 DOWNTO 0);
85      km_cnt : OUT std_logic_vector (9 DOWNTO 0);
86      kp_cnt : OUT std_logic_vector (9 DOWNTO 0);
87      wr_cnt : OUT std_logic_vector (9 DOWNTO 0)
88   );
89   END COMPONENT;
90   COMPONENT dpram624x1
91   PORT (
92      addra : IN std_logic_VECTOR (9 DOWNTO 0);
93      addrb : IN std_logic_VECTOR (9 DOWNTO 0);
94      clka : IN std_logic;
95      clkb : IN std_logic;
96      dina : IN std_logic_VECTOR (0 DOWNTO 0);
97      wea : IN std_logic_VECTOR (0 DOWNTO 0);
98      doutb : OUT std_logic_VECTOR (0 DOWNTO 0)
99   );
100   END COMPONENT;
101   COMPONENT dpram624x31
102   PORT (
103      addra : IN std_logic_VECTOR (9 DOWNTO 0);
104      addrb : IN std_logic_VECTOR (9 DOWNTO 0);
105      clka : IN std_logic;
106      clkb : IN std_logic;
107      dina : IN std_logic_VECTOR (30 DOWNTO 0);
108      wea : IN std_logic_VECTOR (0 DOWNTO 0);
109      doutb : OUT std_logic_VECTOR (30 DOWNTO 0)
110   );
111   END COMPONENT;
112   COMPONENT dpram624x32
113   PORT (
114      addra : IN std_logic_VECTOR (9 DOWNTO 0);
115      addrb : IN std_logic_VECTOR (9 DOWNTO 0);
116      clka : IN std_logic;
117      clkb : IN std_logic;
118      dina : IN std_logic_VECTOR (31 DOWNTO 0);
119      wea : IN std_logic_VECTOR (0 DOWNTO 0);
120      doutb : OUT std_logic_VECTOR (31 DOWNTO 0)
121   );
122   END COMPONENT;
123
124
125BEGIN
126   -- Architecture concurrent statements
127   -- HDL Embedded Text Block 1 eb1
128   -- eb1 1
129   wea_s(0) <= wea; -- wonderful VHDL
130
131   -- HDL Embedded Text Block 2 XOR_CHAIN1
132   -- eb1 1
133   xor1_s <= mt_kk_s XOR ("00000000000"&mt_kk_s(31 downto 11));
134   xor2_s <= xor1_s XOR (xor1_s(24 downto 0)&"0000000" AND X"9D2C5680");
135   xor3_s <= xor2_s XOR (xor2_s(16 downto 0)&"000000000000000" AND X"EFC60000");
136   random <= xor3_s XOR "000000000000000000"&xor3_s(31 downto 18);
137
138   -- HDL Embedded Text Block 3 eb3
139   y_s <= mt_kk31(0)&mt_kp(30 downto 0);
140   mag01_s <= X"00000000" when y_s(0)='0' else X"9908B0DF";
141   mt_kk_s <= mt_km XOR ('0'&y_s(31 downto 1)) XOR mag01_s;
142
143
144   -- Instance port mappings.
145   U_7 : counters
146      GENERIC MAP (
147         M => 397,
148         N => 623
149      )
150      PORT MAP (
151         clk => clk,
152         resetn => resetn,
153         ena => ena,
154         wea => wea,
155         kk_cnt => kk_cnt,
156         km_cnt => km_cnt,
157         kp_cnt => kp_cnt,
158         wr_cnt => wr_cnt
159      );
160   U_0 : dpram624x1
161      PORT MAP (
162         clka => clk,
163         dina => mt_kk_s(31 DOWNTO 31),
164         addra => wr_cnt,
165         wea => wea_s,
166         clkb => clk,
167         addrb => kk_cnt,
168         doutb => mt_kk31
169      );
170   U_1 : dpram624x31
171      PORT MAP (
172         clka => clk,
173         dina => mt_kk_s(30 DOWNTO 0),
174         addra => wr_cnt,
175         wea => wea_s,
176         clkb => clk,
177         addrb => kp_cnt,
178         doutb => mt_kp
179      );
180   U_2 : dpram624x32
181      PORT MAP (
182         clka => clk,
183         dina => mt_kk_s,
184         addra => wr_cnt,
185         wea => wea_s,
186         clkb => clk,
187         addrb => km_cnt,
188         doutb => mt_km
189      );
190
191END struct;
192

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