Root/Examples/ehw4/logic/reg_bank.v

1`timescale 1ns / 1ps
2
3module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg3, reg4, regMT, error, status, max_lev, max_com, control);
4
5  input clk, reset, en, we;
6  
7  input [7:0] wdBus;
8  output [7:0] rdBus;
9  input [4:0] address;
10
11  input [31:0] reg0;
12  input [31:0] reg1;
13  input [31:0] reg2;
14  input [31:0] reg3;
15  input [31:0] reg4;
16  input [31:0] regMT;
17  input [16:0] error;
18  input [7:0] status;
19  output [15:0] max_com;
20  output [7:0] max_lev;
21  output [7:0] control;
22
23
24  reg [7:0] reg_bank [31:0];
25  reg [7:0] rdBus;
26
27 
28
29    // Read control
30    always @(posedge clk)
31      if(reset)
32         rdBus = 8'h00;
33      else begin
34            rdBus = reg_bank[address];
35      end
36
37     // Store Inputs
38    always @(posedge clk)
39     begin
40      if(en) begin
41        reg_bank[0] = reg0[7:0];
42        reg_bank[1] = reg0[15:8];
43        reg_bank[2] = reg0[23:16];
44        reg_bank[3] = reg0[31:24];
45
46        reg_bank[4] = reg1[7:0];
47        reg_bank[5] = reg1[15:8];
48        reg_bank[6] = reg1[23:16];
49        reg_bank[7] = reg1[31:24];
50
51        reg_bank[8] = reg2[7:0];
52        reg_bank[9] = reg2[15:8];
53        reg_bank[10] = reg2[23:16];
54        reg_bank[11] = reg2[31:24];
55
56        reg_bank[12] = reg3[7:0];
57        reg_bank[13] = reg3[15:8];
58        reg_bank[14] = reg3[23:16];
59        reg_bank[15] = reg3[31:24];
60
61        reg_bank[16] = reg4[7:0];
62        reg_bank[17] = reg4[15:8];
63        reg_bank[18] = reg4[23:16];
64        reg_bank[19] = reg4[31:24];
65
66        reg_bank[20] = error[7:0];
67        reg_bank[21] = error[15:8];
68
69        reg_bank[22] = {4'b0, status};
70
71// reg_bank[23] = regMT[7:0];
72// reg_bank[24] = regMT[15:8];
73// reg_bank[25] = regMT[23:16];
74// reg_bank[26] = regMT[31:24];
75      end
76     end
77
78     assign max_com[7:0] = reg_bank[26];
79     assign max_com[15:8] = reg_bank[27];
80     assign max_lev = reg_bank[28];
81     assign control = reg_bank[29];
82
83    // Write control
84    always @(negedge clk)
85      if(we & en) begin
86        case (address)
87          27: reg_bank[26] = wdBus;
88          28: reg_bank[27] = wdBus;
89          29: reg_bank[28] = wdBus;
90          30: reg_bank[29] = wdBus;
91        endcase
92      end
93
94endmodule
95

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