Hardware Design: SIE
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| 1 | /* |
| 2 | * Jz47xx UART support |
| 3 | * |
| 4 | * Options hardcoded to 8N1 |
| 5 | * |
| 6 | * Copyright (c) 2009, yajin <yajin@vm-kernel.org> |
| 7 | * Copyright (c) 2005 - 2008, Ingenic Semiconductor Inc. |
| 8 | * Ingenic Semiconductor, <jlwei@ingenic.cn> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | |
| 27 | #include <jz4740.h> |
| 28 | #include <board.h> |
| 29 | |
| 30 | #undef UART_BASE |
| 31 | #ifndef CFG_UART_BASE |
| 32 | #define UART_BASE UART0_BASE |
| 33 | #else |
| 34 | #define UART_BASE CFG_UART_BASE |
| 35 | #endif |
| 36 | |
| 37 | /****************************************************************************** |
| 38 | * |
| 39 | * serial_init - initialize a channel |
| 40 | * |
| 41 | * This routine initializes the number of data bits, parity |
| 42 | * and set the selected baud rate. Interrupts are disabled. |
| 43 | * Set the modem control signals if the option is selected. |
| 44 | * |
| 45 | * RETURNS: N/A |
| 46 | */ |
| 47 | |
| 48 | static void serial_setbrg(void) |
| 49 | { |
| 50 | volatile u8 *uart_lcr = (volatile u8 *) (UART_BASE + OFF_LCR); |
| 51 | volatile u8 *uart_dlhr = (volatile u8 *) (UART_BASE + OFF_DLHR); |
| 52 | volatile u8 *uart_dllr = (volatile u8 *) (UART_BASE + OFF_DLLR); |
| 53 | u32 baud_div, tmp; |
| 54 | |
| 55 | baud_div = CFG_EXTAL / 16 / CONFIG_BAUDRATE; |
| 56 | tmp = *uart_lcr; |
| 57 | tmp |= UART_LCR_DLAB; |
| 58 | *uart_lcr = tmp; |
| 59 | |
| 60 | *uart_dlhr = (baud_div >> 8) & 0xff; |
| 61 | *uart_dllr = baud_div & 0xff; |
| 62 | |
| 63 | tmp &= ~UART_LCR_DLAB; |
| 64 | *uart_lcr = tmp; |
| 65 | } |
| 66 | |
| 67 | int serial_init(void) |
| 68 | { |
| 69 | volatile u8 *uart_fcr = (volatile u8 *) (UART_BASE + OFF_FCR); |
| 70 | volatile u8 *uart_lcr = (volatile u8 *) (UART_BASE + OFF_LCR); |
| 71 | volatile u8 *uart_ier = (volatile u8 *) (UART_BASE + OFF_IER); |
| 72 | volatile u8 *uart_sircr = (volatile u8 *) (UART_BASE + OFF_SIRCR); |
| 73 | |
| 74 | /* Disable port interrupts while changing hardware */ |
| 75 | *uart_ier = 0; |
| 76 | |
| 77 | /* Disable UART unit function */ |
| 78 | *uart_fcr = ~UART_FCR_UUE; |
| 79 | |
| 80 | /* Set both receiver and transmitter in UART mode (not SIR) */ |
| 81 | *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE); |
| 82 | |
| 83 | /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ |
| 84 | *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1; |
| 85 | |
| 86 | /* Set baud rate */ |
| 87 | serial_setbrg(); |
| 88 | |
| 89 | /* Enable UART unit, enable and clear FIFO */ |
| 90 | *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS; |
| 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | void serial_putc(const char c) |
| 96 | { |
| 97 | volatile u8 *uart_lsr = (volatile u8 *) (UART_BASE + OFF_LSR); |
| 98 | volatile u8 *uart_tdr = (volatile u8 *) (UART_BASE + OFF_TDR); |
| 99 | |
| 100 | if (c == '\n') |
| 101 | serial_putc('\r'); |
| 102 | |
| 103 | /* Wait for fifo to shift out some bytes */ |
| 104 | while (!((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60)); |
| 105 | |
| 106 | *uart_tdr = (u8) c; |
| 107 | } |
| 108 | |
| 109 | void serial_puts(const char *s) |
| 110 | { |
| 111 | while (*s) |
| 112 | { |
| 113 | serial_putc(*s++); |
| 114 | } |
| 115 | } |
| 116 |
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