Root/Examples/hello_nand/build/main.c

1/*
2  * Copyright (c) 2009, yajin <yajin@vm-kernel.org>
3  * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
4  * Author: <jlwei@ingenic.cn>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  */
11
12
13
14#include <jz4740.h>
15#include <board.h>
16
17#define VERSION "0.01"
18
19static void gpio_init(void)
20{
21    __gpio_as_sdram_32bit();
22    __gpio_as_uart0();
23    __gpio_as_nand();
24}
25
26static void nand_enable()
27{
28    REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
29    REG_EMC_SMCR1 = 0x04444400;
30}
31
32/* PLL output clock = EXTAL * NF / (NR * NO)
33 *
34 * NF = FD + 2, NR = RD + 2
35 * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
36 */
37static void pll_init(void)
38{
39    register unsigned int cfcr, plcr1;
40    int n2FR[33] = {
41        0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
42        7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
43        9
44    };
45    int div[5] = { 0, 3, 3, 3, 3 }; /* divisors of I:S:P:M:L */
46    int nf, pllout2;
47
48    cfcr = CPM_CPCCR_CLKOEN |
49        (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
50        (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
51        (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
52        (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
53        (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
54
55    pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
56
57    /* Init USB Host clock, pllout2 must be n*48MHz */
58    REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
59
60    nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
61    plcr1 = ((nf + 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
62        (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
63        (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
64        (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
65        CPM_CPPCR_PLLEN; /* enable PLL */
66
67    /* init PLL */
68    REG_CPM_CPCCR = cfcr;
69    REG_CPM_CPPCR = plcr1;
70
71}
72
73/*
74 * Init SDRAM memory.
75 */
76
77static void sdram_init(void)
78{
79    register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
80
81    unsigned int cas_latency_sdmr[2] = {
82        EMC_SDMR_CAS_2,
83        EMC_SDMR_CAS_3,
84    };
85
86    unsigned int cas_latency_dmcr[2] = {
87        1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
88        2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
89    };
90
91    int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
92
93    cpu_clk = CFG_CPU_SPEED;
94    mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
95
96    //REG_EMC_BCR = 0; /* Disable bus release */
97    REG_EMC_RTCSR = 0; /* Disable clock for counting */
98    REG_EMC_RTCOR = 0;
99    REG_EMC_RTCNT = 0;
100
101    /* Fault DMCR value for mode register setting */
102#define SDRAM_ROW0 11
103#define SDRAM_COL0 8
104#define SDRAM_BANK40 0
105
106    dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
107        ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
108        (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
109        (CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
110        EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
111
112    /* Basic DMCR value */
113    dmcr = ((CFG_SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
114        ((CFG_SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
115        (CFG_SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
116        (CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
117        EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
118
119    /* SDRAM timimg */
120    ns = 1000000000 / mem_clk;
121    tmp = CFG_SDRAM_TRAS / ns;
122    if (tmp < 4)
123        tmp = 4;
124    if (tmp > 11)
125        tmp = 11;
126    dmcr |= ((tmp - 4) << EMC_DMCR_TRAS_BIT);
127    tmp = CFG_SDRAM_RCD / ns;
128    if (tmp > 3)
129        tmp = 3;
130    dmcr |= (tmp << EMC_DMCR_RCD_BIT);
131    tmp = CFG_SDRAM_TPC / ns;
132    if (tmp > 7)
133        tmp = 7;
134    dmcr |= (tmp << EMC_DMCR_TPC_BIT);
135    tmp = CFG_SDRAM_TRWL / ns;
136    if (tmp > 3)
137        tmp = 3;
138    dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
139    tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC) / ns;
140    if (tmp > 14)
141        tmp = 14;
142    dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
143
144    /* SDRAM mode value */
145    sdmode = EMC_SDMR_BT_SEQ |
146        EMC_SDMR_OM_NORMAL |
147        EMC_SDMR_BL_4 | cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
148
149    /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
150    REG_EMC_DMCR = dmcr;
151    REG8(EMC_SDMR0 | sdmode) = 0;
152
153    /* Wait for precharge, > 200us */
154    tmp = (cpu_clk / 1000000) * 1000;
155    while (tmp--);
156
157    /* Stage 2. Enable auto-refresh */
158    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
159
160    tmp = CFG_SDRAM_TREF / ns;
161    tmp = tmp / 64 + 1;
162    if (tmp > 0xff)
163        tmp = 0xff;
164    REG_EMC_RTCOR = tmp;
165    REG_EMC_RTCNT = 0;
166    REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
167
168    /* Wait for number of auto-refresh cycles */
169    tmp = (cpu_clk / 1000000) * 1000;
170    while (tmp--);
171
172    /* Stage 3. Mode Register Set */
173    REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
174    REG8(EMC_SDMR0 | sdmode) = 0;
175
176    /* Set back to basic DMCR value */
177    REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
178
179    /* everything is ok now */
180}
181
182void main_func(void)
183{
184
185    /*
186     * Init gpio, serial, pll and sdram
187     */
188    gpio_init();
189    serial_init();
190    serial_puts("\nJZ x_loader version " VERSION "\n");
191    serial_puts("Copyright 2009 by yajin<yajin@vm-kernel.org>\n");
192    pll_init();
193    sdram_init();
194}
195

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