Root/Examples/sram_gpio/logic/sim/ddr/parameters.v

1///////////////////////////////////////////////////////////////////////////////
2// Copyright (c) 2005 Xilinx, Inc.
3// This design is confidential and proprietary of Xilinx, All Rights Reserved.
4///////////////////////////////////////////////////////////////////////////////
5// ____ ____
6// / /\/ /
7// /___/ \ / Vendor : Xilinx
8// \ \ \/ Version : $Name: mig_v1_73_b0 $
9// \ \ Application : MIG
10// / / Filename : mem_interface_top_parameters_0.v
11// /___/ /\ Date Last Modified : $Date: 2007/06/06 05:44:42 $
12// \ \ / \ Date Created : Mon May 2 2005
13// \___\/\___\
14// Device : Spartan-3/3E/3A
15// Design Name : DDR1 SDRAM
16// Purpose : This module has the parameters used in the design.
17///////////////////////////////////////////////////////////////////////////////
18
19`define data_width 16
20`define data_strobe_width 2
21`define data_mask_width 2
22`define clk_width 1
23`define fifo_16 1
24`define ReadEnable 1
25`define memory_width 8
26`define DatabitsPerReadClock 8
27`define DatabitsPerMask 8
28`define no_of_cs 1
29`define data_mask 1
30`define mask_disable 0
31`define RESET 0
32`define cke_width 1
33`define registered 0
34`define col_ap_width 11
35`define write_pipe_itr 1
36`define write_pipeline 4
37`define top_bottom 0
38`define left_right 1
39`define row_address 13
40`define column_address 10
41`define bank_address 2
42`define spartan3e 1
43`define burst_length 3'b001
44`define burst_type 1'b0
45`define cas_latency_value 3'b110
46`define Operating_mode 5'b00000
47`define load_mode_register 13'b0000001100001
48`define drive_strengh 1'b0
49`define dll_enable 1'b0
50`define ext_load_mode_register 13'b0000000000000
51`define chip_address 1
52`define reset_active_low 1'b1
53`define rcd_count_value 3'b001
54`define ras_count_value 4'b0101
55`define mrd_count_value 1'b0
56`define rp_count_value 3'b001
57`define rfc_count_value 6'b001001
58`define twr_count_value 3'b110
59`define twtr_count_value 3'b100
60`define max_ref_width 11
61`define max_ref_cnt 11'b10000000001
62
63`timescale 1ns/100ps
64                                        
65

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