Root/Examples/sram_gpio/logic/sim/unisims/RAMB16_S2.v

1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
2///////////////////////////////////////////////////////////////////////////////
3// Copyright (c) 1995/2005 Xilinx, Inc.
4// All Right Reserved.
5///////////////////////////////////////////////////////////////////////////////
6// ____ ____
7// / /\/ /
8// /___/ \ / Vendor : Xilinx
9// \ \ \/ Version : 8.1i (I.13)
10// \ \ Description : Xilinx Functional Simulation Library Component
11// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
12// /___/ /\ Filename : RAMB16_S2.v
13// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005
14// \___\/\___\
15//
16// Revision:
17// 03/23/04 - Initial version.
18// End Revision
19
20`ifdef legacy_model
21
22`timescale 1 ps / 1 ps
23
24module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
25
26    parameter INIT = 2'h0;
27    parameter SRVAL = 2'h0;
28    parameter WRITE_MODE = "WRITE_FIRST";
29
30    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
31    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
32    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
34    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
35    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
36    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94
95    output [1:0] DO;
96    reg do0_out, do1_out;
97
98    input [12:0] ADDR;
99    input [1:0] DI;
100    input EN, CLK, WE, SSR;
101
102    reg [18431:0] mem;
103    reg [8:0] count;
104    reg [1:0] wr_mode;
105
106    wire [12:0] addr_int;
107    wire [1:0] di_int;
108    wire en_int, clk_int, we_int, ssr_int;
109
110    tri0 GSR = glbl.GSR;
111
112    always @(GSR)
113    if (GSR) begin
114        assign do0_out = INIT[0];
115        assign do1_out = INIT[1];
116    end
117    else begin
118        deassign do0_out;
119        deassign do1_out;
120    end
121
122    buf b_do_out0 (DO[0], do0_out);
123    buf b_do_out1 (DO[1], do1_out);
124    buf b_addr_0 (addr_int[0], ADDR[0]);
125    buf b_addr_1 (addr_int[1], ADDR[1]);
126    buf b_addr_2 (addr_int[2], ADDR[2]);
127    buf b_addr_3 (addr_int[3], ADDR[3]);
128    buf b_addr_4 (addr_int[4], ADDR[4]);
129    buf b_addr_5 (addr_int[5], ADDR[5]);
130    buf b_addr_6 (addr_int[6], ADDR[6]);
131    buf b_addr_7 (addr_int[7], ADDR[7]);
132    buf b_addr_8 (addr_int[8], ADDR[8]);
133    buf b_addr_9 (addr_int[9], ADDR[9]);
134    buf b_addr_10 (addr_int[10], ADDR[10]);
135    buf b_addr_11 (addr_int[11], ADDR[11]);
136    buf b_addr_12 (addr_int[12], ADDR[12]);
137    buf b_di_0 (di_int[0], DI[0]);
138    buf b_di_1 (di_int[1], DI[1]);
139    buf b_en (en_int, EN);
140    buf b_clk (clk_int, CLK);
141    buf b_we (we_int, WE);
142    buf b_ssr (ssr_int, SSR);
143
144    initial begin
145    for (count = 0; count < 256; count = count + 1) begin
146        mem[count] <= INIT_00[count];
147        mem[256 * 1 + count] <= INIT_01[count];
148        mem[256 * 2 + count] <= INIT_02[count];
149        mem[256 * 3 + count] <= INIT_03[count];
150        mem[256 * 4 + count] <= INIT_04[count];
151        mem[256 * 5 + count] <= INIT_05[count];
152        mem[256 * 6 + count] <= INIT_06[count];
153        mem[256 * 7 + count] <= INIT_07[count];
154        mem[256 * 8 + count] <= INIT_08[count];
155        mem[256 * 9 + count] <= INIT_09[count];
156        mem[256 * 10 + count] <= INIT_0A[count];
157        mem[256 * 11 + count] <= INIT_0B[count];
158        mem[256 * 12 + count] <= INIT_0C[count];
159        mem[256 * 13 + count] <= INIT_0D[count];
160        mem[256 * 14 + count] <= INIT_0E[count];
161        mem[256 * 15 + count] <= INIT_0F[count];
162        mem[256 * 16 + count] <= INIT_10[count];
163        mem[256 * 17 + count] <= INIT_11[count];
164        mem[256 * 18 + count] <= INIT_12[count];
165        mem[256 * 19 + count] <= INIT_13[count];
166        mem[256 * 20 + count] <= INIT_14[count];
167        mem[256 * 21 + count] <= INIT_15[count];
168        mem[256 * 22 + count] <= INIT_16[count];
169        mem[256 * 23 + count] <= INIT_17[count];
170        mem[256 * 24 + count] <= INIT_18[count];
171        mem[256 * 25 + count] <= INIT_19[count];
172        mem[256 * 26 + count] <= INIT_1A[count];
173        mem[256 * 27 + count] <= INIT_1B[count];
174        mem[256 * 28 + count] <= INIT_1C[count];
175        mem[256 * 29 + count] <= INIT_1D[count];
176        mem[256 * 30 + count] <= INIT_1E[count];
177        mem[256 * 31 + count] <= INIT_1F[count];
178        mem[256 * 32 + count] <= INIT_20[count];
179        mem[256 * 33 + count] <= INIT_21[count];
180        mem[256 * 34 + count] <= INIT_22[count];
181        mem[256 * 35 + count] <= INIT_23[count];
182        mem[256 * 36 + count] <= INIT_24[count];
183        mem[256 * 37 + count] <= INIT_25[count];
184        mem[256 * 38 + count] <= INIT_26[count];
185        mem[256 * 39 + count] <= INIT_27[count];
186        mem[256 * 40 + count] <= INIT_28[count];
187        mem[256 * 41 + count] <= INIT_29[count];
188        mem[256 * 42 + count] <= INIT_2A[count];
189        mem[256 * 43 + count] <= INIT_2B[count];
190        mem[256 * 44 + count] <= INIT_2C[count];
191        mem[256 * 45 + count] <= INIT_2D[count];
192        mem[256 * 46 + count] <= INIT_2E[count];
193        mem[256 * 47 + count] <= INIT_2F[count];
194        mem[256 * 48 + count] <= INIT_30[count];
195        mem[256 * 49 + count] <= INIT_31[count];
196        mem[256 * 50 + count] <= INIT_32[count];
197        mem[256 * 51 + count] <= INIT_33[count];
198        mem[256 * 52 + count] <= INIT_34[count];
199        mem[256 * 53 + count] <= INIT_35[count];
200        mem[256 * 54 + count] <= INIT_36[count];
201        mem[256 * 55 + count] <= INIT_37[count];
202        mem[256 * 56 + count] <= INIT_38[count];
203        mem[256 * 57 + count] <= INIT_39[count];
204        mem[256 * 58 + count] <= INIT_3A[count];
205        mem[256 * 59 + count] <= INIT_3B[count];
206        mem[256 * 60 + count] <= INIT_3C[count];
207        mem[256 * 61 + count] <= INIT_3D[count];
208        mem[256 * 62 + count] <= INIT_3E[count];
209        mem[256 * 63 + count] <= INIT_3F[count];
210    end
211    end
212
213    initial begin
214    case (WRITE_MODE)
215        "WRITE_FIRST" : wr_mode <= 2'b00;
216        "READ_FIRST" : wr_mode <= 2'b01;
217        "NO_CHANGE" : wr_mode <= 2'b10;
218        default : begin
219                $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
220                $finish;
221                end
222    endcase
223    end
224
225    always @(posedge clk_int) begin
226    if (en_int == 1'b1) begin
227        if (ssr_int == 1'b1) begin
228        do0_out <= SRVAL[0];
229        do1_out <= SRVAL[1];
230        end
231        else begin
232        if (we_int == 1'b1) begin
233            if (wr_mode == 2'b00) begin
234            do0_out <= di_int[0];
235            do1_out <= di_int[1];
236            end
237            else if (wr_mode == 2'b01) begin
238            do0_out <= mem[addr_int * 2 + 0];
239            do1_out <= mem[addr_int * 2 + 1];
240            end
241            else begin
242            do0_out <= do0_out;
243            do1_out <= do1_out;
244            end
245        end
246        else begin
247            do0_out <= mem[addr_int * 2 + 0];
248            do1_out <= mem[addr_int * 2 + 1];
249        end
250        end
251    end
252    end
253
254    always @(posedge clk_int) begin
255    if (en_int == 1'b1 && we_int == 1'b1) begin
256        mem[addr_int * 2 + 0] <= di_int[0];
257        mem[addr_int * 2 + 1] <= di_int[1];
258    end
259    end
260
261    specify
262    (CLK *> DO) = (100, 100);
263    endspecify
264
265endmodule
266
267`else
268
269// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7.158.1 2007/03/09 18:13:18 patrickp Exp $
270///////////////////////////////////////////////////////////////////////////////
271// Copyright (c) 1995/2005 Xilinx, Inc.
272// All Right Reserved.
273///////////////////////////////////////////////////////////////////////////////
274// ____ ____
275// / /\/ /
276// /___/ \ / Vendor : Xilinx
277// \ \ \/ Version : 8.1i (I.13)
278// \ \ Description : Xilinx Timing Simulation Library Component
279// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM
280// /___/ /\ Filename : RAMB16_S2.v
281// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
282// \___\/\___\
283//
284// Revision:
285// 03/23/04 - Initial version.
286// 03/10/05 - Initialized outputs.
287// End Revision
288
289`timescale 1 ps/1 ps
290
291module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE);
292
293    parameter INIT = 2'h0;
294    parameter SRVAL = 2'h0;
295    parameter WRITE_MODE = "WRITE_FIRST";
296
297    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
298    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
299    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
300    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
301    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
302    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
303    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
304    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
305    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
306    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
307    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
308    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
309    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
310    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
311    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
312    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
313    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
314    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
315    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
316    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
317    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
318    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
319    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
320    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
321    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
322    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
323    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
324    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
325    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
326    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
327    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
328    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
329    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
330    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
331    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
332    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
333    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
334    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
335    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
336    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
337    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
338    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
339    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
340    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
341    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
342    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
343    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
344    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
345    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
346    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
347    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
348    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
349    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
350    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
351    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
352    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
353    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
354    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
355    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
356    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
357    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
358    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
359    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
360    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
361    
362    output [1:0] DO;
363
364    input [12:0] ADDR;
365    input [1:0] DI;
366    input EN, CLK, WE, SSR;
367
368    reg [1:0] do_out = INIT[1:0];
369    
370    reg [1:0] mem [8191:0];
371    
372    reg [8:0] count, countp;
373    reg [1:0] wr_mode;
374
375    wire [12:0] addr_int;
376    wire [1:0] di_int;
377    wire en_int, clk_int, we_int, ssr_int;
378
379    wire di_enable = en_int && we_int;
380    
381    tri0 GSR = glbl.GSR;
382    wire gsr_int;
383
384    buf b_gsr (gsr_int, GSR);
385
386    buf b_do [1:0] (DO, do_out);
387    buf b_addr [12:0] (addr_int, ADDR);
388    buf b_di [1:0] (di_int, DI);
389    buf b_en (en_int, EN);
390    buf b_clk (clk_int, CLK);
391    buf b_ssr (ssr_int, SSR);
392    buf b_we (we_int, WE);
393
394    
395    always @(gsr_int)
396    if (gsr_int) begin
397        assign {do_out} = INIT;
398    end
399    else begin
400        deassign do_out;
401    end
402
403    
404    initial begin
405
406    for (count = 0; count < 128; count = count + 1) begin
407        mem[count] = INIT_00[(count * 2) +: 2];
408        mem[128 * 1 + count] = INIT_01[(count * 2) +: 2];
409        mem[128 * 2 + count] = INIT_02[(count * 2) +: 2];
410        mem[128 * 3 + count] = INIT_03[(count * 2) +: 2];
411        mem[128 * 4 + count] = INIT_04[(count * 2) +: 2];
412        mem[128 * 5 + count] = INIT_05[(count * 2) +: 2];
413        mem[128 * 6 + count] = INIT_06[(count * 2) +: 2];
414        mem[128 * 7 + count] = INIT_07[(count * 2) +: 2];
415        mem[128 * 8 + count] = INIT_08[(count * 2) +: 2];
416        mem[128 * 9 + count] = INIT_09[(count * 2) +: 2];
417        mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
418        mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
419        mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
420        mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
421        mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
422        mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
423        mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
424        mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
425        mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
426        mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
427        mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
428        mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
429        mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
430        mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
431        mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
432        mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
433        mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
434        mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
435        mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
436        mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
437        mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
438        mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
439        mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
440        mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
441        mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
442        mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
443        mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
444        mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
445        mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
446        mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
447        mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
448        mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
449        mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
450        mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
451        mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
452        mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
453        mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
454        mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
455        mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
456        mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
457        mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
458        mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
459        mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
460        mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
461        mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
462        mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
463        mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
464        mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
465        mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
466        mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
467        mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
468        mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
469        mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
470        mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
471    end
472
473    end // initial begin
474    
475
476    initial begin
477    case (WRITE_MODE)
478        "WRITE_FIRST" : wr_mode <= 2'b00;
479        "READ_FIRST" : wr_mode <= 2'b01;
480        "NO_CHANGE" : wr_mode <= 2'b10;
481        default : begin
482                $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE);
483                $finish;
484                end
485    endcase
486    end
487
488
489    always @(posedge clk_int) begin
490
491    if (en_int == 1'b1) begin
492
493        if (ssr_int == 1'b1) begin
494        {do_out} <= #100 SRVAL;
495        end
496        else begin
497        if (we_int == 1'b1) begin
498            if (wr_mode == 2'b00) begin
499            do_out <= #100 di_int;
500            end
501            else if (wr_mode == 2'b01) begin
502            do_out <= #100 mem[addr_int];
503            end
504        end
505        else begin
506            do_out <= #100 mem[addr_int];
507        end
508        end
509
510        // memory
511        if (we_int == 1'b1) begin
512        mem[addr_int] <= di_int;
513        end
514
515    end
516    end
517
518
519endmodule
520
521`endif
522

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