Root/Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S18.v

1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S18.v,v 1.9.158.2 2007/03/09 18:13:18 patrickp Exp $
2///////////////////////////////////////////////////////////////////////////////
3// Copyright (c) 1995/2005 Xilinx, Inc.
4// All Right Reserved.
5///////////////////////////////////////////////////////////////////////////////
6// ____ ____
7// / /\/ /
8// /___/ \ / Vendor : Xilinx
9// \ \ \/ Version : 8.1i (I.13)
10// \ \ Description : Xilinx Functional Simulation Library Component
11// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
12// /___/ /\ Filename : RAMB16_S2_S18.v
13// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005
14// \___\/\___\
15//
16// Revision:
17// 03/23/04 - Initial version.
18// End Revision
19
20`ifdef legacy_model
21
22`timescale 1 ps / 1 ps
23
24module RAMB16_S2_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
25
26    parameter INIT_A = 2'h0;
27    parameter INIT_B = 18'h0;
28    parameter SRVAL_A = 2'h0;
29    parameter SRVAL_B = 18'h0;
30    parameter WRITE_MODE_A = "WRITE_FIRST";
31    parameter WRITE_MODE_B = "WRITE_FIRST";
32    parameter SIM_COLLISION_CHECK = "ALL";
33    localparam SETUP_ALL = 1000;
34    localparam SETUP_READ_FIRST = 3000;
35
36    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
95    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
96    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
97    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
98    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
99    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
100    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
101    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
102    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
103    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
104    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
105    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
106    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
107    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
108
109    output [1:0] DOA;
110    reg [1:0] doa_out;
111    wire doa_out0, doa_out1;
112
113    input [12:0] ADDRA;
114    input [1:0] DIA;
115    input ENA, CLKA, WEA, SSRA;
116
117    output [15:0] DOB;
118    output [1:0] DOPB;
119    reg [15:0] dob_out;
120    reg [1:0] dopb_out;
121    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15;
122    wire dopb0_out, dopb1_out;
123
124    input [9:0] ADDRB;
125    input [15:0] DIB;
126    input [1:0] DIPB;
127    input ENB, CLKB, WEB, SSRB;
128
129    reg [18431:0] mem;
130    reg [8:0] count;
131    reg [1:0] wr_mode_a, wr_mode_b;
132
133    reg [5:0] dmi, dbi;
134    reg [5:0] pmi, pbi;
135
136    wire [12:0] addra_int;
137    reg [12:0] addra_reg;
138    wire [1:0] dia_int;
139    wire ena_int, clka_int, wea_int, ssra_int;
140    reg ena_reg, wea_reg, ssra_reg;
141    wire [9:0] addrb_int;
142    reg [9:0] addrb_reg;
143    wire [15:0] dib_int;
144    wire [1:0] dipb_int;
145    wire enb_int, clkb_int, web_int, ssrb_int;
146    reg display_flag;
147    reg enb_reg, web_reg, ssrb_reg;
148
149    time time_clka, time_clkb;
150    time time_clka_clkb;
151    time time_clkb_clka;
152
153    reg setup_all_a_b;
154    reg setup_all_b_a;
155    reg setup_zero;
156    reg setup_rf_a_b;
157    reg setup_rf_b_a;
158    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
159    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
160    reg address_collision, address_collision_a_b, address_collision_b_a;
161    reg change_clka;
162    reg change_clkb;
163
164    wire [14:0] data_addra_int;
165    wire [14:0] data_addra_reg;
166    wire [14:0] data_addrb_int;
167    wire [14:0] data_addrb_reg;
168    wire [15:0] parity_addra_int;
169    wire [15:0] parity_addra_reg;
170    wire [15:0] parity_addrb_int;
171    wire [15:0] parity_addrb_reg;
172
173    tri0 GSR = glbl.GSR;
174
175    always @(GSR)
176    if (GSR) begin
177        assign doa_out = INIT_A[1:0];
178        assign dob_out = INIT_B[15:0];
179        assign dopb_out = INIT_B[17:16];
180    end
181    else begin
182        deassign doa_out;
183        deassign dob_out;
184        deassign dopb_out;
185    end
186
187    buf b_doa_out0 (doa_out0, doa_out[0]);
188    buf b_doa_out1 (doa_out1, doa_out[1]);
189    buf b_dob_out0 (dob_out0, dob_out[0]);
190    buf b_dob_out1 (dob_out1, dob_out[1]);
191    buf b_dob_out2 (dob_out2, dob_out[2]);
192    buf b_dob_out3 (dob_out3, dob_out[3]);
193    buf b_dob_out4 (dob_out4, dob_out[4]);
194    buf b_dob_out5 (dob_out5, dob_out[5]);
195    buf b_dob_out6 (dob_out6, dob_out[6]);
196    buf b_dob_out7 (dob_out7, dob_out[7]);
197    buf b_dob_out8 (dob_out8, dob_out[8]);
198    buf b_dob_out9 (dob_out9, dob_out[9]);
199    buf b_dob_out10 (dob_out10, dob_out[10]);
200    buf b_dob_out11 (dob_out11, dob_out[11]);
201    buf b_dob_out12 (dob_out12, dob_out[12]);
202    buf b_dob_out13 (dob_out13, dob_out[13]);
203    buf b_dob_out14 (dob_out14, dob_out[14]);
204    buf b_dob_out15 (dob_out15, dob_out[15]);
205    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
206    buf b_dopb_out1 (dopb_out1, dopb_out[1]);
207
208    buf b_doa0 (DOA[0], doa_out0);
209    buf b_doa1 (DOA[1], doa_out1);
210    buf b_dob0 (DOB[0], dob_out0);
211    buf b_dob1 (DOB[1], dob_out1);
212    buf b_dob2 (DOB[2], dob_out2);
213    buf b_dob3 (DOB[3], dob_out3);
214    buf b_dob4 (DOB[4], dob_out4);
215    buf b_dob5 (DOB[5], dob_out5);
216    buf b_dob6 (DOB[6], dob_out6);
217    buf b_dob7 (DOB[7], dob_out7);
218    buf b_dob8 (DOB[8], dob_out8);
219    buf b_dob9 (DOB[9], dob_out9);
220    buf b_dob10 (DOB[10], dob_out10);
221    buf b_dob11 (DOB[11], dob_out11);
222    buf b_dob12 (DOB[12], dob_out12);
223    buf b_dob13 (DOB[13], dob_out13);
224    buf b_dob14 (DOB[14], dob_out14);
225    buf b_dob15 (DOB[15], dob_out15);
226    buf b_dopb0 (DOPB[0], dopb_out0);
227    buf b_dopb1 (DOPB[1], dopb_out1);
228
229    buf b_addra_0 (addra_int[0], ADDRA[0]);
230    buf b_addra_1 (addra_int[1], ADDRA[1]);
231    buf b_addra_2 (addra_int[2], ADDRA[2]);
232    buf b_addra_3 (addra_int[3], ADDRA[3]);
233    buf b_addra_4 (addra_int[4], ADDRA[4]);
234    buf b_addra_5 (addra_int[5], ADDRA[5]);
235    buf b_addra_6 (addra_int[6], ADDRA[6]);
236    buf b_addra_7 (addra_int[7], ADDRA[7]);
237    buf b_addra_8 (addra_int[8], ADDRA[8]);
238    buf b_addra_9 (addra_int[9], ADDRA[9]);
239    buf b_addra_10 (addra_int[10], ADDRA[10]);
240    buf b_addra_11 (addra_int[11], ADDRA[11]);
241    buf b_addra_12 (addra_int[12], ADDRA[12]);
242    buf b_dia_0 (dia_int[0], DIA[0]);
243    buf b_dia_1 (dia_int[1], DIA[1]);
244    buf b_ena (ena_int, ENA);
245    buf b_clka (clka_int, CLKA);
246    buf b_ssra (ssra_int, SSRA);
247    buf b_wea (wea_int, WEA);
248    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
249    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
250    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
251    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
252    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
253    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
254    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
255    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
256    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
257    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
258    buf b_dib_0 (dib_int[0], DIB[0]);
259    buf b_dib_1 (dib_int[1], DIB[1]);
260    buf b_dib_2 (dib_int[2], DIB[2]);
261    buf b_dib_3 (dib_int[3], DIB[3]);
262    buf b_dib_4 (dib_int[4], DIB[4]);
263    buf b_dib_5 (dib_int[5], DIB[5]);
264    buf b_dib_6 (dib_int[6], DIB[6]);
265    buf b_dib_7 (dib_int[7], DIB[7]);
266    buf b_dib_8 (dib_int[8], DIB[8]);
267    buf b_dib_9 (dib_int[9], DIB[9]);
268    buf b_dib_10 (dib_int[10], DIB[10]);
269    buf b_dib_11 (dib_int[11], DIB[11]);
270    buf b_dib_12 (dib_int[12], DIB[12]);
271    buf b_dib_13 (dib_int[13], DIB[13]);
272    buf b_dib_14 (dib_int[14], DIB[14]);
273    buf b_dib_15 (dib_int[15], DIB[15]);
274    buf b_dipb_0 (dipb_int[0], DIPB[0]);
275    buf b_dipb_1 (dipb_int[1], DIPB[1]);
276    buf b_enb (enb_int, ENB);
277    buf b_clkb (clkb_int, CLKB);
278    buf b_ssrb (ssrb_int, SSRB);
279    buf b_web (web_int, WEB);
280
281    initial begin
282    for (count = 0; count < 256; count = count + 1) begin
283        mem[count] <= INIT_00[count];
284        mem[256 * 1 + count] <= INIT_01[count];
285        mem[256 * 2 + count] <= INIT_02[count];
286        mem[256 * 3 + count] <= INIT_03[count];
287        mem[256 * 4 + count] <= INIT_04[count];
288        mem[256 * 5 + count] <= INIT_05[count];
289        mem[256 * 6 + count] <= INIT_06[count];
290        mem[256 * 7 + count] <= INIT_07[count];
291        mem[256 * 8 + count] <= INIT_08[count];
292        mem[256 * 9 + count] <= INIT_09[count];
293        mem[256 * 10 + count] <= INIT_0A[count];
294        mem[256 * 11 + count] <= INIT_0B[count];
295        mem[256 * 12 + count] <= INIT_0C[count];
296        mem[256 * 13 + count] <= INIT_0D[count];
297        mem[256 * 14 + count] <= INIT_0E[count];
298        mem[256 * 15 + count] <= INIT_0F[count];
299        mem[256 * 16 + count] <= INIT_10[count];
300        mem[256 * 17 + count] <= INIT_11[count];
301        mem[256 * 18 + count] <= INIT_12[count];
302        mem[256 * 19 + count] <= INIT_13[count];
303        mem[256 * 20 + count] <= INIT_14[count];
304        mem[256 * 21 + count] <= INIT_15[count];
305        mem[256 * 22 + count] <= INIT_16[count];
306        mem[256 * 23 + count] <= INIT_17[count];
307        mem[256 * 24 + count] <= INIT_18[count];
308        mem[256 * 25 + count] <= INIT_19[count];
309        mem[256 * 26 + count] <= INIT_1A[count];
310        mem[256 * 27 + count] <= INIT_1B[count];
311        mem[256 * 28 + count] <= INIT_1C[count];
312        mem[256 * 29 + count] <= INIT_1D[count];
313        mem[256 * 30 + count] <= INIT_1E[count];
314        mem[256 * 31 + count] <= INIT_1F[count];
315        mem[256 * 32 + count] <= INIT_20[count];
316        mem[256 * 33 + count] <= INIT_21[count];
317        mem[256 * 34 + count] <= INIT_22[count];
318        mem[256 * 35 + count] <= INIT_23[count];
319        mem[256 * 36 + count] <= INIT_24[count];
320        mem[256 * 37 + count] <= INIT_25[count];
321        mem[256 * 38 + count] <= INIT_26[count];
322        mem[256 * 39 + count] <= INIT_27[count];
323        mem[256 * 40 + count] <= INIT_28[count];
324        mem[256 * 41 + count] <= INIT_29[count];
325        mem[256 * 42 + count] <= INIT_2A[count];
326        mem[256 * 43 + count] <= INIT_2B[count];
327        mem[256 * 44 + count] <= INIT_2C[count];
328        mem[256 * 45 + count] <= INIT_2D[count];
329        mem[256 * 46 + count] <= INIT_2E[count];
330        mem[256 * 47 + count] <= INIT_2F[count];
331        mem[256 * 48 + count] <= INIT_30[count];
332        mem[256 * 49 + count] <= INIT_31[count];
333        mem[256 * 50 + count] <= INIT_32[count];
334        mem[256 * 51 + count] <= INIT_33[count];
335        mem[256 * 52 + count] <= INIT_34[count];
336        mem[256 * 53 + count] <= INIT_35[count];
337        mem[256 * 54 + count] <= INIT_36[count];
338        mem[256 * 55 + count] <= INIT_37[count];
339        mem[256 * 56 + count] <= INIT_38[count];
340        mem[256 * 57 + count] <= INIT_39[count];
341        mem[256 * 58 + count] <= INIT_3A[count];
342        mem[256 * 59 + count] <= INIT_3B[count];
343        mem[256 * 60 + count] <= INIT_3C[count];
344        mem[256 * 61 + count] <= INIT_3D[count];
345        mem[256 * 62 + count] <= INIT_3E[count];
346        mem[256 * 63 + count] <= INIT_3F[count];
347        mem[256 * 64 + count] <= INITP_00[count];
348        mem[256 * 65 + count] <= INITP_01[count];
349        mem[256 * 66 + count] <= INITP_02[count];
350        mem[256 * 67 + count] <= INITP_03[count];
351        mem[256 * 68 + count] <= INITP_04[count];
352        mem[256 * 69 + count] <= INITP_05[count];
353        mem[256 * 70 + count] <= INITP_06[count];
354        mem[256 * 71 + count] <= INITP_07[count];
355    end
356    address_collision <= 0;
357    address_collision_a_b <= 0;
358    address_collision_b_a <= 0;
359    change_clka <= 0;
360    change_clkb <= 0;
361    data_collision <= 0;
362    data_collision_a_b <= 0;
363    data_collision_b_a <= 0;
364    memory_collision <= 0;
365    memory_collision_a_b <= 0;
366    memory_collision_b_a <= 0;
367    setup_all_a_b <= 0;
368    setup_all_b_a <= 0;
369    setup_zero <= 0;
370    setup_rf_a_b <= 0;
371    setup_rf_b_a <= 0;
372    end
373
374    assign data_addra_int = addra_int * 2;
375    assign data_addra_reg = addra_reg * 2;
376    assign data_addrb_int = addrb_int * 16;
377    assign data_addrb_reg = addrb_reg * 16;
378    assign parity_addrb_int = 16384 + addrb_int * 2;
379    assign parity_addrb_reg = 16384 + addrb_reg * 2;
380
381
382    initial begin
383
384    display_flag = 1;
385
386    case (SIM_COLLISION_CHECK)
387
388        "NONE" : begin
389                 assign setup_all_a_b = 1'b0;
390                     assign setup_all_b_a = 1'b0;
391                     assign setup_zero = 1'b0;
392                     assign setup_rf_a_b = 1'b0;
393                     assign setup_rf_b_a = 1'b0;
394                     assign display_flag = 0;
395                 end
396        "WARNING_ONLY" : begin
397                         assign data_collision = 2'b00;
398                             assign data_collision_a_b = 2'b00;
399                             assign data_collision_b_a = 2'b00;
400                             assign memory_collision = 1'b0;
401                             assign memory_collision_a_b = 1'b0;
402                             assign memory_collision_b_a = 1'b0;
403                         end
404        "GENERATE_X_ONLY" : begin
405                            assign display_flag = 0;
406                            end
407        "ALL" : ;
408        default : begin
409                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
410                  $finish;
411                  end
412
413    endcase // case(SIM_COLLISION_CHECK)
414
415    end // initial begin
416
417
418    always @(posedge clka_int) begin
419    time_clka = $time;
420    #0 time_clkb_clka = time_clka - time_clkb;
421    change_clka = ~change_clka;
422    end
423
424    always @(posedge clkb_int) begin
425    time_clkb = $time;
426    #0 time_clka_clkb = time_clkb - time_clka;
427    change_clkb = ~change_clkb;
428    end
429
430    always @(change_clkb) begin
431    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
432        setup_all_a_b = 1;
433    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
434        setup_rf_a_b = 1;
435    end
436
437    always @(change_clka) begin
438    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
439        setup_all_b_a = 1;
440    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
441        setup_rf_b_a = 1;
442    end
443
444    always @(change_clkb or change_clka) begin
445    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
446        setup_zero = 1;
447    end
448
449    always @(posedge setup_zero) begin
450    if ((ena_int == 1) && (wea_int == 1) &&
451        (enb_int == 1) && (web_int == 1) &&
452        (data_addra_int[14:4] == data_addrb_int[14:4]))
453        memory_collision <= 1;
454    end
455
456    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
457    if ((ena_reg == 1) && (wea_reg == 1) &&
458        (enb_int == 1) && (web_int == 1) &&
459        (data_addra_reg[14:4] == data_addrb_int[14:4]))
460        memory_collision_a_b <= 1;
461    end
462
463    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
464    if ((ena_int == 1) && (wea_int == 1) &&
465        (enb_reg == 1) && (web_reg == 1) &&
466        (data_addra_int[14:4] == data_addrb_reg[14:4]))
467        memory_collision_b_a <= 1;
468    end
469
470    always @(posedge setup_all_a_b) begin
471    if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin
472    if ((ena_reg == 1) && (enb_int == 1)) begin
473        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
474        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
475        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
476        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
477// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
478// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
479// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
480        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
481        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
482        6'b101011 : begin display_wa_wb; end
483        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
484// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
485        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
486        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
487// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
488        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
489        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
490// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
491        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
492        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
493        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
494        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
495// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
496// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
497// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
498        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
499        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
500        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
501        endcase
502    end
503    end
504    setup_all_a_b <= 0;
505    end
506
507
508    always @(posedge setup_all_b_a) begin
509    if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin
510    if ((ena_int == 1) && (enb_reg == 1)) begin
511        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
512        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
513// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
514        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
515        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
516// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
517        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
518        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
519        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
520        6'b101011 : begin display_wa_wb; end
521        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
522        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
523        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
524        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
525        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
526        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
527        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
528        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
529        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
530        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
531        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
532        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
533// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
534// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
535// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
536        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
537        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
538        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
539        endcase
540    end
541    end
542    setup_all_b_a <= 0;
543    end
544
545
546    always @(posedge setup_zero) begin
547    if (data_addra_int[14:4] == data_addrb_int[14:4]) begin
548    if ((ena_int == 1) && (enb_int == 1)) begin
549        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
550        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
551        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
552        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
553        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
554        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
555        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
556        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
557        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
558        6'b101011 : begin display_wa_wb; end
559        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
560// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
561        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
562        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
563// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
564        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
565        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
566// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
567        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
568        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
569        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
570        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
571// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
572// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
573// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
574        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
575        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
576        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
577        endcase
578    end
579    end
580    setup_zero <= 0;
581    end
582
583    task display_ra_wb;
584    begin
585    if (display_flag)
586        $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
587    end
588    endtask
589
590    task display_wa_rb;
591    begin
592    if (display_flag)
593        $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
594    end
595    endtask
596
597    task display_wa_wb;
598    begin
599    if (display_flag)
600        $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
601    end
602    endtask
603
604
605    always @(posedge setup_rf_a_b) begin
606    if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin
607    if ((ena_reg == 1) && (enb_int == 1)) begin
608        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
609// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
610// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
611// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
612        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
613        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
614        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
615// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
616// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
617// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
618// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
619// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
620// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
621// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
622// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
623// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
624// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
625// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
626// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
627// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
628// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
629// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
630        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
631        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
632        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
633// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
634// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
635// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
636        endcase
637    end
638    end
639    setup_rf_a_b <= 0;
640    end
641
642
643    always @(posedge setup_rf_b_a) begin
644    if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin
645    if ((ena_int == 1) && (enb_reg == 1)) begin
646        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
647// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
648        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
649// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
650// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
651        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
652// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
653// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
654        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
655// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
656// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
657        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
658// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
659// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
660        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
661// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
662// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
663        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
664// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
665// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
666// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
667// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
668// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
669// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
670// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
671// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
672// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
673// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
674        endcase
675    end
676    end
677    setup_rf_b_a <= 0;
678    end
679
680
681    always @(posedge clka_int) begin
682    addra_reg <= addra_int;
683    ena_reg <= ena_int;
684    ssra_reg <= ssra_int;
685    wea_reg <= wea_int;
686    end
687
688    always @(posedge clkb_int) begin
689    addrb_reg <= addrb_int;
690    enb_reg <= enb_int;
691    ssrb_reg <= ssrb_int;
692    web_reg <= web_int;
693    end
694
695    // Data
696    always @(posedge memory_collision) begin
697    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
698        mem[data_addra_int + dmi] <= 1'bX;
699    end
700    memory_collision <= 0;
701    end
702
703    always @(posedge memory_collision_a_b) begin
704    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
705        mem[data_addra_reg + dmi] <= 1'bX;
706    end
707    memory_collision_a_b <= 0;
708    end
709
710    always @(posedge memory_collision_b_a) begin
711    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
712        mem[data_addra_int + dmi] <= 1'bX;
713    end
714    memory_collision_b_a <= 0;
715    end
716
717    always @(posedge data_collision[1]) begin
718    if (ssra_int == 0) begin
719        doa_out <= 2'bX;
720    end
721    data_collision[1] <= 0;
722    end
723
724    always @(posedge data_collision[0]) begin
725    if (ssrb_int == 0) begin
726        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
727        dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX;
728        end
729    end
730    data_collision[0] <= 0;
731    end
732
733    always @(posedge data_collision_a_b[1]) begin
734    if (ssra_reg == 0) begin
735        doa_out <= 2'bX;
736    end
737    data_collision_a_b[1] <= 0;
738    end
739
740    always @(posedge data_collision_a_b[0]) begin
741    if (ssrb_int == 0) begin
742        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
743        dob_out[data_addra_reg[3 : 0] + dbi] <= 1'bX;
744        end
745    end
746    data_collision_a_b[0] <= 0;
747    end
748
749    always @(posedge data_collision_b_a[1]) begin
750    if (ssra_int == 0) begin
751        doa_out <= 2'bX;
752    end
753    data_collision_b_a[1] <= 0;
754    end
755
756    always @(posedge data_collision_b_a[0]) begin
757    if (ssrb_reg == 0) begin
758        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
759        dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX;
760        end
761    end
762    data_collision_b_a[0] <= 0;
763    end
764
765
766    initial begin
767    case (WRITE_MODE_A)
768        "WRITE_FIRST" : wr_mode_a <= 2'b00;
769        "READ_FIRST" : wr_mode_a <= 2'b01;
770        "NO_CHANGE" : wr_mode_a <= 2'b10;
771        default : begin
772                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
773                $finish;
774                end
775    endcase
776    end
777
778    initial begin
779    case (WRITE_MODE_B)
780        "WRITE_FIRST" : wr_mode_b <= 2'b00;
781        "READ_FIRST" : wr_mode_b <= 2'b01;
782        "NO_CHANGE" : wr_mode_b <= 2'b10;
783        default : begin
784                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
785                $finish;
786                end
787    endcase
788    end
789
790    // Port A
791    always @(posedge clka_int) begin
792    if (ena_int == 1'b1) begin
793        if (ssra_int == 1'b1) begin
794        doa_out[0] <= SRVAL_A[0];
795        doa_out[1] <= SRVAL_A[1];
796        end
797        else begin
798        if (wea_int == 1'b1) begin
799            if (wr_mode_a == 2'b00) begin
800            doa_out <= dia_int;
801            end
802            else if (wr_mode_a == 2'b01) begin
803            doa_out[0] <= mem[data_addra_int + 0];
804            doa_out[1] <= mem[data_addra_int + 1];
805            end
806        end
807        else begin
808            doa_out[0] <= mem[data_addra_int + 0];
809            doa_out[1] <= mem[data_addra_int + 1];
810        end
811        end
812    end
813    end
814
815    always @(posedge clka_int) begin
816    if (ena_int == 1'b1 && wea_int == 1'b1) begin
817        mem[data_addra_int + 0] <= dia_int[0];
818        mem[data_addra_int + 1] <= dia_int[1];
819    end
820    end
821
822    // Port B
823    always @(posedge clkb_int) begin
824    if (enb_int == 1'b1) begin
825        if (ssrb_int == 1'b1) begin
826        dob_out[0] <= SRVAL_B[0];
827        dob_out[1] <= SRVAL_B[1];
828        dob_out[2] <= SRVAL_B[2];
829        dob_out[3] <= SRVAL_B[3];
830        dob_out[4] <= SRVAL_B[4];
831        dob_out[5] <= SRVAL_B[5];
832        dob_out[6] <= SRVAL_B[6];
833        dob_out[7] <= SRVAL_B[7];
834        dob_out[8] <= SRVAL_B[8];
835        dob_out[9] <= SRVAL_B[9];
836        dob_out[10] <= SRVAL_B[10];
837        dob_out[11] <= SRVAL_B[11];
838        dob_out[12] <= SRVAL_B[12];
839        dob_out[13] <= SRVAL_B[13];
840        dob_out[14] <= SRVAL_B[14];
841        dob_out[15] <= SRVAL_B[15];
842        dopb_out[0] <= SRVAL_B[16];
843        dopb_out[1] <= SRVAL_B[17];
844        end
845        else begin
846        if (web_int == 1'b1) begin
847            if (wr_mode_b == 2'b00) begin
848            dob_out <= dib_int;
849            dopb_out <= dipb_int;
850            end
851            else if (wr_mode_b == 2'b01) begin
852            dob_out[0] <= mem[data_addrb_int + 0];
853            dob_out[1] <= mem[data_addrb_int + 1];
854            dob_out[2] <= mem[data_addrb_int + 2];
855            dob_out[3] <= mem[data_addrb_int + 3];
856            dob_out[4] <= mem[data_addrb_int + 4];
857            dob_out[5] <= mem[data_addrb_int + 5];
858            dob_out[6] <= mem[data_addrb_int + 6];
859            dob_out[7] <= mem[data_addrb_int + 7];
860            dob_out[8] <= mem[data_addrb_int + 8];
861            dob_out[9] <= mem[data_addrb_int + 9];
862            dob_out[10] <= mem[data_addrb_int + 10];
863            dob_out[11] <= mem[data_addrb_int + 11];
864            dob_out[12] <= mem[data_addrb_int + 12];
865            dob_out[13] <= mem[data_addrb_int + 13];
866            dob_out[14] <= mem[data_addrb_int + 14];
867            dob_out[15] <= mem[data_addrb_int + 15];
868            dopb_out[0] <= mem[parity_addrb_int + 0];
869            dopb_out[1] <= mem[parity_addrb_int + 1];
870            end
871        end
872        else begin
873            dob_out[0] <= mem[data_addrb_int + 0];
874            dob_out[1] <= mem[data_addrb_int + 1];
875            dob_out[2] <= mem[data_addrb_int + 2];
876            dob_out[3] <= mem[data_addrb_int + 3];
877            dob_out[4] <= mem[data_addrb_int + 4];
878            dob_out[5] <= mem[data_addrb_int + 5];
879            dob_out[6] <= mem[data_addrb_int + 6];
880            dob_out[7] <= mem[data_addrb_int + 7];
881            dob_out[8] <= mem[data_addrb_int + 8];
882            dob_out[9] <= mem[data_addrb_int + 9];
883            dob_out[10] <= mem[data_addrb_int + 10];
884            dob_out[11] <= mem[data_addrb_int + 11];
885            dob_out[12] <= mem[data_addrb_int + 12];
886            dob_out[13] <= mem[data_addrb_int + 13];
887            dob_out[14] <= mem[data_addrb_int + 14];
888            dob_out[15] <= mem[data_addrb_int + 15];
889            dopb_out[0] <= mem[parity_addrb_int + 0];
890            dopb_out[1] <= mem[parity_addrb_int + 1];
891        end
892        end
893    end
894    end
895
896    always @(posedge clkb_int) begin
897    if (enb_int == 1'b1 && web_int == 1'b1) begin
898        mem[data_addrb_int + 0] <= dib_int[0];
899        mem[data_addrb_int + 1] <= dib_int[1];
900        mem[data_addrb_int + 2] <= dib_int[2];
901        mem[data_addrb_int + 3] <= dib_int[3];
902        mem[data_addrb_int + 4] <= dib_int[4];
903        mem[data_addrb_int + 5] <= dib_int[5];
904        mem[data_addrb_int + 6] <= dib_int[6];
905        mem[data_addrb_int + 7] <= dib_int[7];
906        mem[data_addrb_int + 8] <= dib_int[8];
907        mem[data_addrb_int + 9] <= dib_int[9];
908        mem[data_addrb_int + 10] <= dib_int[10];
909        mem[data_addrb_int + 11] <= dib_int[11];
910        mem[data_addrb_int + 12] <= dib_int[12];
911        mem[data_addrb_int + 13] <= dib_int[13];
912        mem[data_addrb_int + 14] <= dib_int[14];
913        mem[data_addrb_int + 15] <= dib_int[15];
914        mem[parity_addrb_int + 0] <= dipb_int[0];
915        mem[parity_addrb_int + 1] <= dipb_int[1];
916    end
917    end
918
919    specify
920    (CLKA *> DOA) = (100, 100);
921    (CLKB *> DOB) = (100, 100);
922    (CLKB *> DOPB) = (100, 100);
923    endspecify
924
925endmodule
926
927`else
928
929// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S18.v,v 1.9.158.2 2007/03/09 18:13:18 patrickp Exp $
930///////////////////////////////////////////////////////////////////////////////
931// Copyright (c) 1995/2005 Xilinx, Inc.
932// All Right Reserved.
933///////////////////////////////////////////////////////////////////////////////
934// ____ ____
935// / /\/ /
936// /___/ \ / Vendor : Xilinx
937// \ \ \/ Version : 8.1i (I.13)
938// \ \ Description : Xilinx Timing Simulation Library Component
939// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
940// /___/ /\ Filename : RAMB16_S2_S18.v
941// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
942// \___\/\___\
943//
944// Revision:
945// 03/23/04 - Initial version.
946// 03/10/05 - Initialized outputs.
947// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281).
948// End Revision
949
950`timescale 1 ps/1 ps
951
952module RAMB16_S2_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
953
954    parameter INIT_A = 2'h0;
955    parameter INIT_B = 18'h0;
956    parameter SRVAL_A = 2'h0;
957    parameter SRVAL_B = 18'h0;
958    parameter WRITE_MODE_A = "WRITE_FIRST";
959    parameter WRITE_MODE_B = "WRITE_FIRST";
960    parameter SIM_COLLISION_CHECK = "ALL";
961    localparam SETUP_ALL = 1000;
962    localparam SETUP_READ_FIRST = 3000;
963
964    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
965    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
966    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
967    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
968    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
969    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
970    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
971    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
972    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
973    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
974    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
975    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
976    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
977    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
978    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
979    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
980    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
981    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
982    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
983    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
984    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
985    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
986    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
987    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
988    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
989    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
990    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
991    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
992    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
993    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
994    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
995    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
996    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
997    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
998    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
999    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1000    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1001    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1002    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1003    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1004    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1005    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1006    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1007    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1008    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1009    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1010    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1011    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1012    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1013    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1014    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1015    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1016    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1017    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1018    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1019    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1020    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1021    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1022    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1023    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1024    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1025    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1026    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1027    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1028    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1029    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1030    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1031    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1032    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1033    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1034    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1035    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1036
1037    output [1:0] DOA;
1038    output [15:0] DOB;
1039    output [1:0] DOPB;
1040
1041    input [12:0] ADDRA;
1042    input [1:0] DIA;
1043    input ENA, CLKA, WEA, SSRA;
1044    input [9:0] ADDRB;
1045    input [15:0] DIB;
1046    input [1:0] DIPB;
1047    input ENB, CLKB, WEB, SSRB;
1048
1049    reg [1:0] doa_out = INIT_A[1:0];
1050    reg [15:0] dob_out = INIT_B[15:0];
1051    reg [1:0] dopb_out = INIT_B[17:16];
1052    
1053    reg [15:0] mem [1023:0];
1054    reg [1:0] memp [1023:0];
1055    
1056    reg [8:0] count, countp;
1057    reg [1:0] wr_mode_a, wr_mode_b;
1058
1059    reg [5:0] dmi, dbi;
1060    reg [5:0] pmi, pbi;
1061
1062    wire [12:0] addra_int;
1063    reg [12:0] addra_reg;
1064    wire [1:0] dia_int;
1065    wire ena_int, clka_int, wea_int, ssra_int;
1066    reg ena_reg, wea_reg, ssra_reg;
1067    wire [9:0] addrb_int;
1068    reg [9:0] addrb_reg;
1069    wire [15:0] dib_int;
1070    wire [1:0] dipb_int;
1071    wire enb_int, clkb_int, web_int, ssrb_int;
1072    reg display_flag, output_flag;
1073    reg enb_reg, web_reg, ssrb_reg;
1074
1075    time time_clka, time_clkb;
1076    time time_clka_clkb;
1077    time time_clkb_clka;
1078
1079    reg setup_all_a_b;
1080    reg setup_all_b_a;
1081    reg setup_zero;
1082    reg setup_rf_a_b;
1083    reg setup_rf_b_a;
1084    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
1085    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
1086    reg change_clka;
1087    reg change_clkb;
1088
1089    wire [14:0] data_addra_int;
1090    wire [14:0] data_addra_reg;
1091    wire [14:0] data_addrb_int;
1092    wire [14:0] data_addrb_reg;
1093
1094    wire dia_enable = ena_int && wea_int;
1095    wire dib_enable = enb_int && web_int;
1096
1097    tri0 GSR = glbl.GSR;
1098    wire gsr_int;
1099
1100    buf b_gsr (gsr_int, GSR);
1101
1102    buf b_doa [1:0] (DOA, doa_out);
1103    buf b_addra [12:0] (addra_int, ADDRA);
1104    buf b_dia [1:0] (dia_int, DIA);
1105    buf b_ena (ena_int, ENA);
1106    buf b_clka (clka_int, CLKA);
1107    buf b_ssra (ssra_int, SSRA);
1108    buf b_wea (wea_int, WEA);
1109
1110    buf b_dob [15:0] (DOB, dob_out);
1111    buf b_dopb [1:0] (DOPB, dopb_out);
1112    buf b_addrb [9:0] (addrb_int, ADDRB);
1113    buf b_dib [15:0] (dib_int, DIB);
1114    buf b_dipb [1:0] (dipb_int, DIPB);
1115    buf b_enb (enb_int, ENB);
1116    buf b_clkb (clkb_int, CLKB);
1117    buf b_ssrb (ssrb_int, SSRB);
1118    buf b_web (web_int, WEB);
1119
1120    
1121    always @(gsr_int)
1122    if (gsr_int) begin
1123        assign {doa_out} = INIT_A;
1124        assign {dopb_out, dob_out} = INIT_B;
1125    end
1126    else begin
1127        deassign doa_out;
1128        deassign dob_out;
1129        deassign dopb_out;
1130    end
1131
1132    
1133    initial begin
1134
1135    for (count = 0; count < 16; count = count + 1) begin
1136        mem[count] = INIT_00[(count * 16) +: 16];
1137        mem[16 * 1 + count] = INIT_01[(count * 16) +: 16];
1138        mem[16 * 2 + count] = INIT_02[(count * 16) +: 16];
1139        mem[16 * 3 + count] = INIT_03[(count * 16) +: 16];
1140        mem[16 * 4 + count] = INIT_04[(count * 16) +: 16];
1141        mem[16 * 5 + count] = INIT_05[(count * 16) +: 16];
1142        mem[16 * 6 + count] = INIT_06[(count * 16) +: 16];
1143        mem[16 * 7 + count] = INIT_07[(count * 16) +: 16];
1144        mem[16 * 8 + count] = INIT_08[(count * 16) +: 16];
1145        mem[16 * 9 + count] = INIT_09[(count * 16) +: 16];
1146        mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16];
1147        mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16];
1148        mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16];
1149        mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16];
1150        mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16];
1151        mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16];
1152        mem[16 * 16 + count] = INIT_10[(count * 16) +: 16];
1153        mem[16 * 17 + count] = INIT_11[(count * 16) +: 16];
1154        mem[16 * 18 + count] = INIT_12[(count * 16) +: 16];
1155        mem[16 * 19 + count] = INIT_13[(count * 16) +: 16];
1156        mem[16 * 20 + count] = INIT_14[(count * 16) +: 16];
1157        mem[16 * 21 + count] = INIT_15[(count * 16) +: 16];
1158        mem[16 * 22 + count] = INIT_16[(count * 16) +: 16];
1159        mem[16 * 23 + count] = INIT_17[(count * 16) +: 16];
1160        mem[16 * 24 + count] = INIT_18[(count * 16) +: 16];
1161        mem[16 * 25 + count] = INIT_19[(count * 16) +: 16];
1162        mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16];
1163        mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16];
1164        mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16];
1165        mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16];
1166        mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16];
1167        mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16];
1168        mem[16 * 32 + count] = INIT_20[(count * 16) +: 16];
1169        mem[16 * 33 + count] = INIT_21[(count * 16) +: 16];
1170        mem[16 * 34 + count] = INIT_22[(count * 16) +: 16];
1171        mem[16 * 35 + count] = INIT_23[(count * 16) +: 16];
1172        mem[16 * 36 + count] = INIT_24[(count * 16) +: 16];
1173        mem[16 * 37 + count] = INIT_25[(count * 16) +: 16];
1174        mem[16 * 38 + count] = INIT_26[(count * 16) +: 16];
1175        mem[16 * 39 + count] = INIT_27[(count * 16) +: 16];
1176        mem[16 * 40 + count] = INIT_28[(count * 16) +: 16];
1177        mem[16 * 41 + count] = INIT_29[(count * 16) +: 16];
1178        mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16];
1179        mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16];
1180        mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16];
1181        mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16];
1182        mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16];
1183        mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16];
1184        mem[16 * 48 + count] = INIT_30[(count * 16) +: 16];
1185        mem[16 * 49 + count] = INIT_31[(count * 16) +: 16];
1186        mem[16 * 50 + count] = INIT_32[(count * 16) +: 16];
1187        mem[16 * 51 + count] = INIT_33[(count * 16) +: 16];
1188        mem[16 * 52 + count] = INIT_34[(count * 16) +: 16];
1189        mem[16 * 53 + count] = INIT_35[(count * 16) +: 16];
1190        mem[16 * 54 + count] = INIT_36[(count * 16) +: 16];
1191        mem[16 * 55 + count] = INIT_37[(count * 16) +: 16];
1192        mem[16 * 56 + count] = INIT_38[(count * 16) +: 16];
1193        mem[16 * 57 + count] = INIT_39[(count * 16) +: 16];
1194        mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16];
1195        mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16];
1196        mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16];
1197        mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16];
1198        mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16];
1199        mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16];
1200    end
1201
1202// initiate parity start
1203    for (countp = 0; countp < 128; countp = countp + 1) begin
1204        memp[countp] = INITP_00[(countp * 2) +: 2];
1205        memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2];
1206        memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2];
1207        memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2];
1208        memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2];
1209        memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2];
1210        memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2];
1211        memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2];
1212    end
1213// initiate parity end
1214    
1215    change_clka <= 0;
1216    change_clkb <= 0;
1217    data_collision <= 0;
1218    data_collision_a_b <= 0;
1219    data_collision_b_a <= 0;
1220    memory_collision <= 0;
1221    memory_collision_a_b <= 0;
1222    memory_collision_b_a <= 0;
1223    setup_all_a_b <= 0;
1224    setup_all_b_a <= 0;
1225    setup_zero <= 0;
1226    setup_rf_a_b <= 0;
1227    setup_rf_b_a <= 0;
1228    end
1229
1230    assign data_addra_int = addra_int * 2;
1231    assign data_addra_reg = addra_reg * 2;
1232    assign data_addrb_int = addrb_int * 16;
1233    assign data_addrb_reg = addrb_reg * 16;
1234
1235
1236    initial begin
1237
1238    display_flag = 1;
1239    output_flag = 1;
1240    
1241    case (SIM_COLLISION_CHECK)
1242
1243        "NONE" : begin
1244                 output_flag = 0;
1245                     display_flag = 0;
1246                 end
1247        "WARNING_ONLY" : output_flag = 0;
1248        "GENERATE_X_ONLY" : display_flag = 0;
1249        "ALL" : ;
1250
1251        default : begin
1252                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
1253                  $finish;
1254                  end
1255
1256    endcase // case(SIM_COLLISION_CHECK)
1257
1258    end // initial begin
1259
1260    
1261    always @(posedge clka_int) begin
1262    if ((output_flag || display_flag)) begin
1263        time_clka = $time;
1264        #0 time_clkb_clka = time_clka - time_clkb;
1265        change_clka = ~change_clka;
1266    end
1267    end
1268    
1269    always @(posedge clkb_int) begin
1270    if ((output_flag || display_flag)) begin
1271        time_clkb = $time;
1272        #0 time_clka_clkb = time_clkb - time_clka;
1273        change_clkb = ~change_clkb;
1274    end
1275    end
1276    
1277    always @(change_clkb) begin
1278    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
1279        setup_all_a_b = 1;
1280    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
1281        setup_rf_a_b = 1;
1282    end
1283
1284    always @(change_clka) begin
1285    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
1286        setup_all_b_a = 1;
1287    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
1288        setup_rf_b_a = 1;
1289    end
1290
1291    always @(change_clkb or change_clka) begin
1292    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
1293        setup_zero = 1;
1294    end
1295
1296    always @(posedge setup_zero) begin
1297    if ((ena_int == 1) && (wea_int == 1) &&
1298        (enb_int == 1) && (web_int == 1) &&
1299        (data_addra_int[14:4] == data_addrb_int[14:4]))
1300        memory_collision <= 1;
1301    end
1302
1303    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
1304    if ((ena_reg == 1) && (wea_reg == 1) &&
1305        (enb_int == 1) && (web_int == 1) &&
1306        (data_addra_reg[14:4] == data_addrb_int[14:4]))
1307        memory_collision_a_b <= 1;
1308    end
1309
1310    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
1311    if ((ena_int == 1) && (wea_int == 1) &&
1312        (enb_reg == 1) && (web_reg == 1) &&
1313        (data_addra_int[14:4] == data_addrb_reg[14:4]))
1314        memory_collision_b_a <= 1;
1315    end
1316
1317    always @(posedge setup_all_a_b) begin
1318    if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin
1319    if ((ena_reg == 1) && (enb_int == 1)) begin
1320        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1321        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1322        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1323        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1324// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1325// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1326// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1327        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1328        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1329        6'b101011 : begin display_wa_wb; end
1330        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1331// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1332        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1333        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1334// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1335        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1336        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1337// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1338        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1339        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1340        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1341        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1342// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1343// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1344// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1345        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1346        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1347        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1348        endcase
1349    end
1350    end
1351    setup_all_a_b <= 0;
1352    end
1353
1354
1355    always @(posedge setup_all_b_a) begin
1356    if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin
1357    if ((ena_int == 1) && (enb_reg == 1)) begin
1358        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1359        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1360// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1361        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1362        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1363// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1364        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1365        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1366        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1367        6'b101011 : begin display_wa_wb; end
1368        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1369        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1370        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1371        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1372        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1373        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1374        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1375        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1376        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1377        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1378        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1379        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1380// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1381// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1382// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1383        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1384        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1385        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1386        endcase
1387    end
1388    end
1389    setup_all_b_a <= 0;
1390    end
1391
1392
1393    always @(posedge setup_zero) begin
1394    if (data_addra_int[14:4] == data_addrb_int[14:4]) begin
1395    if ((ena_int == 1) && (enb_int == 1)) begin
1396        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
1397        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
1398        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
1399        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
1400        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
1401        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
1402        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
1403        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
1404        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
1405        6'b101011 : begin display_wa_wb; end
1406        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
1407// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
1408        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
1409        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
1410// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
1411        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
1412        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
1413// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
1414        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
1415        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
1416        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
1417        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
1418// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
1419// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
1420// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
1421        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
1422        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
1423        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
1424        endcase
1425    end
1426    end
1427    setup_zero <= 0;
1428    end
1429
1430    task display_ra_wb;
1431    begin
1432    if (display_flag)
1433        $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
1434    end
1435    endtask
1436
1437    task display_wa_rb;
1438    begin
1439    if (display_flag)
1440        $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
1441    end
1442    endtask
1443
1444    task display_wa_wb;
1445    begin
1446    if (display_flag)
1447        $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
1448    end
1449    endtask
1450
1451
1452    always @(posedge setup_rf_a_b) begin
1453    if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin
1454    if ((ena_reg == 1) && (enb_int == 1)) begin
1455        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1456// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1457// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1458// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1459        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1460        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1461        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1462// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1463// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1464// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1465// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1466// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1467// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1468// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1469// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1470// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1471// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1472// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1473// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1474// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1475// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1476// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1477        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1478        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1479        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1480// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1481// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1482// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1483        endcase
1484    end
1485    end
1486    setup_rf_a_b <= 0;
1487    end
1488
1489
1490    always @(posedge setup_rf_b_a) begin
1491    if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin
1492    if ((ena_int == 1) && (enb_reg == 1)) begin
1493        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1494// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1495        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1496// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1497// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1498        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1499// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1500// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1501        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1502// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1503// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1504        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1505// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1506// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1507        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1508// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1509// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1510        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1511// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1512// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1513// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1514// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1515// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1516// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1517// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1518// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1519// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1520// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1521        endcase
1522    end
1523    end
1524    setup_rf_b_a <= 0;
1525    end
1526
1527
1528    always @(posedge clka_int) begin
1529    if ((output_flag || display_flag)) begin
1530        addra_reg <= addra_int;
1531        ena_reg <= ena_int;
1532        ssra_reg <= ssra_int;
1533        wea_reg <= wea_int;
1534    end
1535    end
1536    
1537    always @(posedge clkb_int) begin
1538    if ((output_flag || display_flag)) begin
1539        addrb_reg <= addrb_int;
1540        enb_reg <= enb_int;
1541        ssrb_reg <= ssrb_int;
1542        web_reg <= web_int;
1543    end
1544    end
1545    
1546        
1547    // Data
1548    always @(posedge memory_collision) begin
1549    if ((output_flag || display_flag)) begin
1550        mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2] <= 2'bx;
1551        memory_collision <= 0;
1552    end
1553    
1554    end
1555
1556    always @(posedge memory_collision_a_b) begin
1557    if ((output_flag || display_flag)) begin
1558        mem[addra_reg[12:3]][addra_reg[2:0] * 2 +: 2] <= 2'bx;
1559        memory_collision_a_b <= 0;
1560    end
1561    end
1562    
1563    always @(posedge memory_collision_b_a) begin
1564    if ((output_flag || display_flag)) begin
1565        mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2] <= 2'bx;
1566        memory_collision_b_a <= 0;
1567    end
1568    end
1569    
1570    always @(posedge data_collision[1]) begin
1571    if (ssra_int == 0 && output_flag) begin
1572        doa_out <= #100 2'bX;
1573    end
1574    data_collision[1] <= 0;
1575    end
1576
1577    always @(posedge data_collision[0]) begin
1578    if (ssrb_int == 0 && output_flag) begin
1579        dob_out[addra_int[2:0] * 2 +: 2] <= #100 2'bX;
1580    end
1581    data_collision[0] <= 0;
1582    end
1583
1584    always @(posedge data_collision_a_b[1]) begin
1585    if (ssra_reg == 0 && output_flag) begin
1586        doa_out <= #100 2'bX;
1587    end
1588    data_collision_a_b[1] <= 0;
1589    end
1590
1591    always @(posedge data_collision_a_b[0]) begin
1592    if (ssrb_int == 0 && output_flag) begin
1593        dob_out[addra_reg[2:0] * 2 +: 2] <= #100 2'bX;
1594    end
1595    data_collision_a_b[0] <= 0;
1596    end
1597
1598    always @(posedge data_collision_b_a[1]) begin
1599    if (ssra_int == 0 && output_flag) begin
1600        doa_out <= #100 2'bX;
1601    end
1602    data_collision_b_a[1] <= 0;
1603    end
1604
1605    always @(posedge data_collision_b_a[0]) begin
1606    if (ssrb_reg == 0 && output_flag) begin
1607        dob_out[addra_int[2:0] * 2 +: 2] <= #100 2'bX;
1608    end
1609    data_collision_b_a[0] <= 0;
1610    end
1611
1612
1613    initial begin
1614    case (WRITE_MODE_A)
1615        "WRITE_FIRST" : wr_mode_a <= 2'b00;
1616        "READ_FIRST" : wr_mode_a <= 2'b01;
1617        "NO_CHANGE" : wr_mode_a <= 2'b10;
1618        default : begin
1619                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
1620                $finish;
1621                end
1622    endcase
1623    end
1624
1625    initial begin
1626    case (WRITE_MODE_B)
1627        "WRITE_FIRST" : wr_mode_b <= 2'b00;
1628        "READ_FIRST" : wr_mode_b <= 2'b01;
1629        "NO_CHANGE" : wr_mode_b <= 2'b10;
1630        default : begin
1631                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
1632                $finish;
1633                end
1634    endcase
1635    end
1636
1637
1638    // Port A
1639    always @(posedge clka_int) begin
1640
1641    if (ena_int == 1'b1) begin
1642
1643        if (ssra_int == 1'b1) begin
1644        {doa_out} <= #100 SRVAL_A;
1645        end
1646        else begin
1647        if (wea_int == 1'b1) begin
1648            if (wr_mode_a == 2'b00) begin
1649            doa_out <= #100 dia_int;
1650            end
1651            else if (wr_mode_a == 2'b01) begin
1652
1653            doa_out <= #100 mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2];
1654
1655            end
1656        end
1657        else begin
1658
1659            doa_out <= #100 mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2];
1660            
1661        end
1662        end
1663
1664        // memory
1665        if (wea_int == 1'b1) begin
1666        mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2] <= dia_int;
1667        end
1668        
1669    end
1670    end
1671
1672
1673    // Port B
1674    always @(posedge clkb_int) begin
1675
1676    if (enb_int == 1'b1) begin
1677
1678        if (ssrb_int == 1'b1) begin
1679        {dopb_out, dob_out} <= #100 SRVAL_B;
1680        end
1681        else begin
1682        if (web_int == 1'b1) begin
1683            if (wr_mode_b == 2'b00) begin
1684            dob_out <= #100 dib_int;
1685            dopb_out <= #100 dipb_int;
1686            end
1687            else if (wr_mode_b == 2'b01) begin
1688            dob_out <= #100 mem[addrb_int];
1689            dopb_out <= #100 memp[addrb_int];
1690            end
1691        end
1692        else begin
1693            dob_out <= #100 mem[addrb_int];
1694            dopb_out <= #100 memp[addrb_int];
1695        end
1696        end
1697
1698        // memory
1699        if (web_int == 1'b1) begin
1700        mem[addrb_int] <= dib_int;
1701        memp[addrb_int] <= dipb_int;
1702        end
1703
1704    end
1705    end
1706
1707
1708endmodule
1709
1710`endif
1711

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