Root/Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S2.v

1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S2.v,v 1.10.158.2 2007/03/09 18:13:18 patrickp Exp $
2///////////////////////////////////////////////////////////////////////////////
3// Copyright (c) 1995/2005 Xilinx, Inc.
4// All Right Reserved.
5///////////////////////////////////////////////////////////////////////////////
6// ____ ____
7// / /\/ /
8// /___/ \ / Vendor : Xilinx
9// \ \ \/ Version : 8.1i (I.13)
10// \ \ Description : Xilinx Functional Simulation Library Component
11// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
12// /___/ /\ Filename : RAMB16_S2_S2.v
13// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005
14// \___\/\___\
15//
16// Revision:
17// 03/23/04 - Initial version.
18// End Revision
19
20`ifdef legacy_model
21
22`timescale 1 ps / 1 ps
23
24module RAMB16_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
25
26    parameter INIT_A = 2'h0;
27    parameter INIT_B = 2'h0;
28    parameter SRVAL_A = 2'h0;
29    parameter SRVAL_B = 2'h0;
30    parameter WRITE_MODE_A = "WRITE_FIRST";
31    parameter WRITE_MODE_B = "WRITE_FIRST";
32    parameter SIM_COLLISION_CHECK = "ALL";
33    localparam SETUP_ALL = 1000;
34    localparam SETUP_READ_FIRST = 3000;
35
36    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
95    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
96    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
97    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
98    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
99    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
100
101    output [1:0] DOA;
102    reg [1:0] doa_out;
103    wire doa_out0, doa_out1;
104
105    input [12:0] ADDRA;
106    input [1:0] DIA;
107    input ENA, CLKA, WEA, SSRA;
108
109    output [1:0] DOB;
110    reg [1:0] dob_out;
111    wire dob_out0, dob_out1;
112
113    input [12:0] ADDRB;
114    input [1:0] DIB;
115    input ENB, CLKB, WEB, SSRB;
116
117    reg [18431:0] mem;
118    reg [8:0] count;
119    reg [1:0] wr_mode_a, wr_mode_b;
120
121    reg [5:0] dmi, dbi;
122    reg [5:0] pmi, pbi;
123
124    wire [12:0] addra_int;
125    reg [12:0] addra_reg;
126    wire [1:0] dia_int;
127    wire ena_int, clka_int, wea_int, ssra_int;
128    reg ena_reg, wea_reg, ssra_reg;
129    wire [12:0] addrb_int;
130    reg [12:0] addrb_reg;
131    wire [1:0] dib_int;
132    wire enb_int, clkb_int, web_int, ssrb_int;
133    reg display_flag;
134    reg enb_reg, web_reg, ssrb_reg;
135
136    time time_clka, time_clkb;
137    time time_clka_clkb;
138    time time_clkb_clka;
139
140    reg setup_all_a_b;
141    reg setup_all_b_a;
142    reg setup_zero;
143    reg setup_rf_a_b;
144    reg setup_rf_b_a;
145    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
146    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
147    reg address_collision, address_collision_a_b, address_collision_b_a;
148    reg change_clka;
149    reg change_clkb;
150
151    wire [14:0] data_addra_int;
152    wire [14:0] data_addra_reg;
153    wire [14:0] data_addrb_int;
154    wire [14:0] data_addrb_reg;
155    wire [15:0] parity_addra_int;
156    wire [15:0] parity_addra_reg;
157    wire [15:0] parity_addrb_int;
158    wire [15:0] parity_addrb_reg;
159
160    tri0 GSR = glbl.GSR;
161
162    always @(GSR)
163    if (GSR) begin
164        assign doa_out = INIT_A[1:0];
165        assign dob_out = INIT_B[1:0];
166    end
167    else begin
168        deassign doa_out;
169        deassign dob_out;
170    end
171
172    buf b_doa_out0 (doa_out0, doa_out[0]);
173    buf b_doa_out1 (doa_out1, doa_out[1]);
174    buf b_dob_out0 (dob_out0, dob_out[0]);
175    buf b_dob_out1 (dob_out1, dob_out[1]);
176
177    buf b_doa0 (DOA[0], doa_out0);
178    buf b_doa1 (DOA[1], doa_out1);
179    buf b_dob0 (DOB[0], dob_out0);
180    buf b_dob1 (DOB[1], dob_out1);
181
182    buf b_addra_0 (addra_int[0], ADDRA[0]);
183    buf b_addra_1 (addra_int[1], ADDRA[1]);
184    buf b_addra_2 (addra_int[2], ADDRA[2]);
185    buf b_addra_3 (addra_int[3], ADDRA[3]);
186    buf b_addra_4 (addra_int[4], ADDRA[4]);
187    buf b_addra_5 (addra_int[5], ADDRA[5]);
188    buf b_addra_6 (addra_int[6], ADDRA[6]);
189    buf b_addra_7 (addra_int[7], ADDRA[7]);
190    buf b_addra_8 (addra_int[8], ADDRA[8]);
191    buf b_addra_9 (addra_int[9], ADDRA[9]);
192    buf b_addra_10 (addra_int[10], ADDRA[10]);
193    buf b_addra_11 (addra_int[11], ADDRA[11]);
194    buf b_addra_12 (addra_int[12], ADDRA[12]);
195    buf b_dia_0 (dia_int[0], DIA[0]);
196    buf b_dia_1 (dia_int[1], DIA[1]);
197    buf b_ena (ena_int, ENA);
198    buf b_clka (clka_int, CLKA);
199    buf b_ssra (ssra_int, SSRA);
200    buf b_wea (wea_int, WEA);
201    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
202    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
203    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
204    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
205    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
206    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
207    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
208    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
209    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
210    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
211    buf b_addrb_10 (addrb_int[10], ADDRB[10]);
212    buf b_addrb_11 (addrb_int[11], ADDRB[11]);
213    buf b_addrb_12 (addrb_int[12], ADDRB[12]);
214    buf b_dib_0 (dib_int[0], DIB[0]);
215    buf b_dib_1 (dib_int[1], DIB[1]);
216    buf b_enb (enb_int, ENB);
217    buf b_clkb (clkb_int, CLKB);
218    buf b_ssrb (ssrb_int, SSRB);
219    buf b_web (web_int, WEB);
220
221    initial begin
222    for (count = 0; count < 256; count = count + 1) begin
223        mem[count] <= INIT_00[count];
224        mem[256 * 1 + count] <= INIT_01[count];
225        mem[256 * 2 + count] <= INIT_02[count];
226        mem[256 * 3 + count] <= INIT_03[count];
227        mem[256 * 4 + count] <= INIT_04[count];
228        mem[256 * 5 + count] <= INIT_05[count];
229        mem[256 * 6 + count] <= INIT_06[count];
230        mem[256 * 7 + count] <= INIT_07[count];
231        mem[256 * 8 + count] <= INIT_08[count];
232        mem[256 * 9 + count] <= INIT_09[count];
233        mem[256 * 10 + count] <= INIT_0A[count];
234        mem[256 * 11 + count] <= INIT_0B[count];
235        mem[256 * 12 + count] <= INIT_0C[count];
236        mem[256 * 13 + count] <= INIT_0D[count];
237        mem[256 * 14 + count] <= INIT_0E[count];
238        mem[256 * 15 + count] <= INIT_0F[count];
239        mem[256 * 16 + count] <= INIT_10[count];
240        mem[256 * 17 + count] <= INIT_11[count];
241        mem[256 * 18 + count] <= INIT_12[count];
242        mem[256 * 19 + count] <= INIT_13[count];
243        mem[256 * 20 + count] <= INIT_14[count];
244        mem[256 * 21 + count] <= INIT_15[count];
245        mem[256 * 22 + count] <= INIT_16[count];
246        mem[256 * 23 + count] <= INIT_17[count];
247        mem[256 * 24 + count] <= INIT_18[count];
248        mem[256 * 25 + count] <= INIT_19[count];
249        mem[256 * 26 + count] <= INIT_1A[count];
250        mem[256 * 27 + count] <= INIT_1B[count];
251        mem[256 * 28 + count] <= INIT_1C[count];
252        mem[256 * 29 + count] <= INIT_1D[count];
253        mem[256 * 30 + count] <= INIT_1E[count];
254        mem[256 * 31 + count] <= INIT_1F[count];
255        mem[256 * 32 + count] <= INIT_20[count];
256        mem[256 * 33 + count] <= INIT_21[count];
257        mem[256 * 34 + count] <= INIT_22[count];
258        mem[256 * 35 + count] <= INIT_23[count];
259        mem[256 * 36 + count] <= INIT_24[count];
260        mem[256 * 37 + count] <= INIT_25[count];
261        mem[256 * 38 + count] <= INIT_26[count];
262        mem[256 * 39 + count] <= INIT_27[count];
263        mem[256 * 40 + count] <= INIT_28[count];
264        mem[256 * 41 + count] <= INIT_29[count];
265        mem[256 * 42 + count] <= INIT_2A[count];
266        mem[256 * 43 + count] <= INIT_2B[count];
267        mem[256 * 44 + count] <= INIT_2C[count];
268        mem[256 * 45 + count] <= INIT_2D[count];
269        mem[256 * 46 + count] <= INIT_2E[count];
270        mem[256 * 47 + count] <= INIT_2F[count];
271        mem[256 * 48 + count] <= INIT_30[count];
272        mem[256 * 49 + count] <= INIT_31[count];
273        mem[256 * 50 + count] <= INIT_32[count];
274        mem[256 * 51 + count] <= INIT_33[count];
275        mem[256 * 52 + count] <= INIT_34[count];
276        mem[256 * 53 + count] <= INIT_35[count];
277        mem[256 * 54 + count] <= INIT_36[count];
278        mem[256 * 55 + count] <= INIT_37[count];
279        mem[256 * 56 + count] <= INIT_38[count];
280        mem[256 * 57 + count] <= INIT_39[count];
281        mem[256 * 58 + count] <= INIT_3A[count];
282        mem[256 * 59 + count] <= INIT_3B[count];
283        mem[256 * 60 + count] <= INIT_3C[count];
284        mem[256 * 61 + count] <= INIT_3D[count];
285        mem[256 * 62 + count] <= INIT_3E[count];
286        mem[256 * 63 + count] <= INIT_3F[count];
287    end
288    address_collision <= 0;
289    address_collision_a_b <= 0;
290    address_collision_b_a <= 0;
291    change_clka <= 0;
292    change_clkb <= 0;
293    data_collision <= 0;
294    data_collision_a_b <= 0;
295    data_collision_b_a <= 0;
296    memory_collision <= 0;
297    memory_collision_a_b <= 0;
298    memory_collision_b_a <= 0;
299    setup_all_a_b <= 0;
300    setup_all_b_a <= 0;
301    setup_zero <= 0;
302    setup_rf_a_b <= 0;
303    setup_rf_b_a <= 0;
304    end
305
306    assign data_addra_int = addra_int * 2;
307    assign data_addra_reg = addra_reg * 2;
308    assign data_addrb_int = addrb_int * 2;
309    assign data_addrb_reg = addrb_reg * 2;
310
311
312    initial begin
313
314    display_flag = 1;
315
316    case (SIM_COLLISION_CHECK)
317
318        "NONE" : begin
319                 assign setup_all_a_b = 1'b0;
320                     assign setup_all_b_a = 1'b0;
321                     assign setup_zero = 1'b0;
322                     assign setup_rf_a_b = 1'b0;
323                     assign setup_rf_b_a = 1'b0;
324                     assign display_flag = 0;
325                 end
326        "WARNING_ONLY" : begin
327                         assign data_collision = 2'b00;
328                             assign data_collision_a_b = 2'b00;
329                             assign data_collision_b_a = 2'b00;
330                             assign memory_collision = 1'b0;
331                             assign memory_collision_a_b = 1'b0;
332                             assign memory_collision_b_a = 1'b0;
333                         end
334        "GENERATE_X_ONLY" : begin
335                            assign display_flag = 0;
336                            end
337        "ALL" : ;
338        default : begin
339                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
340                  $finish;
341                  end
342
343    endcase // case(SIM_COLLISION_CHECK)
344
345    end // initial begin
346
347
348    always @(posedge clka_int) begin
349    time_clka = $time;
350    #0 time_clkb_clka = time_clka - time_clkb;
351    change_clka = ~change_clka;
352    end
353
354    always @(posedge clkb_int) begin
355    time_clkb = $time;
356    #0 time_clka_clkb = time_clkb - time_clka;
357    change_clkb = ~change_clkb;
358    end
359
360    always @(change_clkb) begin
361    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
362        setup_all_a_b = 1;
363    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
364        setup_rf_a_b = 1;
365    end
366
367    always @(change_clka) begin
368    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
369        setup_all_b_a = 1;
370    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
371        setup_rf_b_a = 1;
372    end
373
374    always @(change_clkb or change_clka) begin
375    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
376        setup_zero = 1;
377    end
378
379    always @(posedge setup_zero) begin
380    if ((ena_int == 1) && (wea_int == 1) &&
381        (enb_int == 1) && (web_int == 1) &&
382        (data_addra_int[14:1] == data_addrb_int[14:1]))
383        memory_collision <= 1;
384    end
385
386    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
387    if ((ena_reg == 1) && (wea_reg == 1) &&
388        (enb_int == 1) && (web_int == 1) &&
389        (data_addra_reg[14:1] == data_addrb_int[14:1]))
390        memory_collision_a_b <= 1;
391    end
392
393    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
394    if ((ena_int == 1) && (wea_int == 1) &&
395        (enb_reg == 1) && (web_reg == 1) &&
396        (data_addra_int[14:1] == data_addrb_reg[14:1]))
397        memory_collision_b_a <= 1;
398    end
399
400    always @(posedge setup_all_a_b) begin
401    if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
402    if ((ena_reg == 1) && (enb_int == 1)) begin
403        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
404        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
405        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
406        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
407// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
408// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
409// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
410        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
411        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
412        6'b101011 : begin display_wa_wb; end
413        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
414// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
415        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
416        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
417// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
418        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
419        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
420// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
421        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
422        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
423        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
424        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
425// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
426// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
427// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
428        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
429        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
430        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
431        endcase
432    end
433    end
434    setup_all_a_b <= 0;
435    end
436
437
438    always @(posedge setup_all_b_a) begin
439    if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
440    if ((ena_int == 1) && (enb_reg == 1)) begin
441        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
442        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
443// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
444        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
445        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
446// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
447        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
448        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
449        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
450        6'b101011 : begin display_wa_wb; end
451        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
452        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
453        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
454        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
455        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
456        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
457        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
458        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
459        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
460        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
461        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
462        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
463// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
464// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
465// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
466        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
467        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
468        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
469        endcase
470    end
471    end
472    setup_all_b_a <= 0;
473    end
474
475
476    always @(posedge setup_zero) begin
477    if (data_addra_int[14:1] == data_addrb_int[14:1]) begin
478    if ((ena_int == 1) && (enb_int == 1)) begin
479        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
480        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
481        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
482        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
483        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
484        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
485        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
486        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
487        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
488        6'b101011 : begin display_wa_wb; end
489        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
490// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
491        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
492        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
493// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
494        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
495        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
496// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
497        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
498        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
499        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
500        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
501// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
502// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
503// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
504        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
505        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
506        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
507        endcase
508    end
509    end
510    setup_zero <= 0;
511    end
512
513    task display_ra_wb;
514    begin
515    if (display_flag)
516        $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
517    end
518    endtask
519
520    task display_wa_rb;
521    begin
522    if (display_flag)
523        $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
524    end
525    endtask
526
527    task display_wa_wb;
528    begin
529    if (display_flag)
530        $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
531    end
532    endtask
533
534
535    always @(posedge setup_rf_a_b) begin
536    if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
537    if ((ena_reg == 1) && (enb_int == 1)) begin
538        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
539// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
540// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
541// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
542        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
543        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
544        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
545// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
546// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
547// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
548// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
549// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
550// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
551// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
552// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
553// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
554// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
555// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
556// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
557// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
558// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
559// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
560        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
561        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
562        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
563// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
564// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
565// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
566        endcase
567    end
568    end
569    setup_rf_a_b <= 0;
570    end
571
572
573    always @(posedge setup_rf_b_a) begin
574    if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
575    if ((ena_int == 1) && (enb_reg == 1)) begin
576        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
577// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
578        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
579// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
580// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
581        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
582// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
583// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
584        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
585// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
586// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
587        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
588// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
589// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
590        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
591// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
592// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
593        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
594// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
595// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
596// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
597// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
598// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
599// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
600// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
601// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
602// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
603// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
604        endcase
605    end
606    end
607    setup_rf_b_a <= 0;
608    end
609
610
611    always @(posedge clka_int) begin
612    addra_reg <= addra_int;
613    ena_reg <= ena_int;
614    ssra_reg <= ssra_int;
615    wea_reg <= wea_int;
616    end
617
618    always @(posedge clkb_int) begin
619    addrb_reg <= addrb_int;
620    enb_reg <= enb_int;
621    ssrb_reg <= ssrb_int;
622    web_reg <= web_int;
623    end
624
625    // Data
626    always @(posedge memory_collision) begin
627    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
628        mem[data_addra_int + dmi] <= 1'bX;
629    end
630    memory_collision <= 0;
631    end
632
633    always @(posedge memory_collision_a_b) begin
634    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
635        mem[data_addra_reg + dmi] <= 1'bX;
636    end
637    memory_collision_a_b <= 0;
638    end
639
640    always @(posedge memory_collision_b_a) begin
641    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
642        mem[data_addra_int + dmi] <= 1'bX;
643    end
644    memory_collision_b_a <= 0;
645    end
646
647    always @(posedge data_collision[1]) begin
648    if (ssra_int == 0) begin
649        doa_out <= 2'bX;
650    end
651    data_collision[1] <= 0;
652    end
653
654    always @(posedge data_collision[0]) begin
655    if (ssrb_int == 0) begin
656        dob_out <= 2'bX;
657    end
658    data_collision[0] <= 0;
659    end
660
661    always @(posedge data_collision_a_b[1]) begin
662    if (ssra_reg == 0) begin
663        doa_out <= 2'bX;
664    end
665    data_collision_a_b[1] <= 0;
666    end
667
668    always @(posedge data_collision_a_b[0]) begin
669    if (ssrb_int == 0) begin
670        dob_out <= 2'bX;
671    end
672    data_collision_a_b[0] <= 0;
673    end
674
675    always @(posedge data_collision_b_a[1]) begin
676    if (ssra_int == 0) begin
677        doa_out <= 2'bX;
678    end
679    data_collision_b_a[1] <= 0;
680    end
681
682    always @(posedge data_collision_b_a[0]) begin
683    if (ssrb_reg == 0) begin
684    dob_out <= 2'bX;
685    end
686    data_collision_b_a[0] <= 0;
687    end
688
689
690    initial begin
691    case (WRITE_MODE_A)
692        "WRITE_FIRST" : wr_mode_a <= 2'b00;
693        "READ_FIRST" : wr_mode_a <= 2'b01;
694        "NO_CHANGE" : wr_mode_a <= 2'b10;
695        default : begin
696                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
697                $finish;
698                end
699    endcase
700    end
701
702    initial begin
703    case (WRITE_MODE_B)
704        "WRITE_FIRST" : wr_mode_b <= 2'b00;
705        "READ_FIRST" : wr_mode_b <= 2'b01;
706        "NO_CHANGE" : wr_mode_b <= 2'b10;
707        default : begin
708                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
709                $finish;
710                end
711    endcase
712    end
713
714    // Port A
715    always @(posedge clka_int) begin
716    if (ena_int == 1'b1) begin
717        if (ssra_int == 1'b1) begin
718        doa_out[0] <= SRVAL_A[0];
719        doa_out[1] <= SRVAL_A[1];
720        end
721        else begin
722        if (wea_int == 1'b1) begin
723            if (wr_mode_a == 2'b00) begin
724            doa_out <= dia_int;
725            end
726            else if (wr_mode_a == 2'b01) begin
727            doa_out[0] <= mem[data_addra_int + 0];
728            doa_out[1] <= mem[data_addra_int + 1];
729            end
730        end
731        else begin
732            doa_out[0] <= mem[data_addra_int + 0];
733            doa_out[1] <= mem[data_addra_int + 1];
734        end
735        end
736    end
737    end
738
739    always @(posedge clka_int) begin
740    if (ena_int == 1'b1 && wea_int == 1'b1) begin
741        mem[data_addra_int + 0] <= dia_int[0];
742        mem[data_addra_int + 1] <= dia_int[1];
743    end
744    end
745
746    // Port B
747    always @(posedge clkb_int) begin
748    if (enb_int == 1'b1) begin
749        if (ssrb_int == 1'b1) begin
750        dob_out[0] <= SRVAL_B[0];
751        dob_out[1] <= SRVAL_B[1];
752        end
753        else begin
754        if (web_int == 1'b1) begin
755            if (wr_mode_b == 2'b00) begin
756            dob_out <= dib_int;
757            end
758            else if (wr_mode_b == 2'b01) begin
759            dob_out[0] <= mem[data_addrb_int + 0];
760            dob_out[1] <= mem[data_addrb_int + 1];
761            end
762        end
763        else begin
764            dob_out[0] <= mem[data_addrb_int + 0];
765            dob_out[1] <= mem[data_addrb_int + 1];
766        end
767        end
768    end
769    end
770
771    always @(posedge clkb_int) begin
772    if (enb_int == 1'b1 && web_int == 1'b1) begin
773        mem[data_addrb_int + 0] <= dib_int[0];
774        mem[data_addrb_int + 1] <= dib_int[1];
775    end
776    end
777
778    specify
779    (CLKA *> DOA) = (100, 100);
780    (CLKB *> DOB) = (100, 100);
781    endspecify
782
783endmodule
784
785`else
786
787// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S2.v,v 1.10.158.2 2007/03/09 18:13:18 patrickp Exp $
788///////////////////////////////////////////////////////////////////////////////
789// Copyright (c) 1995/2005 Xilinx, Inc.
790// All Right Reserved.
791///////////////////////////////////////////////////////////////////////////////
792// ____ ____
793// / /\/ /
794// /___/ \ / Vendor : Xilinx
795// \ \ \/ Version : 8.1i (I.13)
796// \ \ Description : Xilinx Timing Simulation Library Component
797// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
798// /___/ /\ Filename : RAMB16_S2_S2.v
799// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
800// \___\/\___\
801//
802// Revision:
803// 03/23/04 - Initial version.
804// 03/10/05 - Initialized outputs.
805// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281).
806// End Revision
807
808`timescale 1 ps/1 ps
809
810module RAMB16_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB);
811
812    parameter INIT_A = 2'h0;
813    parameter INIT_B = 2'h0;
814    parameter SRVAL_A = 2'h0;
815    parameter SRVAL_B = 2'h0;
816    parameter WRITE_MODE_A = "WRITE_FIRST";
817    parameter WRITE_MODE_B = "WRITE_FIRST";
818    parameter SIM_COLLISION_CHECK = "ALL";
819    localparam SETUP_ALL = 1000;
820    localparam SETUP_READ_FIRST = 3000;
821
822    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
823    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
824    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
825    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
826    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
827    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
828    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
829    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
830    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
831    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
832    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
833    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
834    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
835    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
836    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
837    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
838    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
839    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
840    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
841    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
842    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
843    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
844    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
845    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
846    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
847    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
848    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
849    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
850    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
851    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
852    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
853    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
854    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
855    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
856    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
857    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
858    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
859    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
860    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
861    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
862    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
863    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
864    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
865    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
866    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
867    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
868    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
869    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
870    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
871    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
872    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
873    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
874    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
875    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
876    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
877    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
878    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
879    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
880    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
881    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
882    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
883    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
884    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
885    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
886
887    output [1:0] DOA;
888    output [1:0] DOB;
889
890    input [12:0] ADDRA;
891    input [1:0] DIA;
892    input ENA, CLKA, WEA, SSRA;
893    input [12:0] ADDRB;
894    input [1:0] DIB;
895    input ENB, CLKB, WEB, SSRB;
896
897    reg [1:0] doa_out = INIT_A[1:0];
898    reg [1:0] dob_out = INIT_B[1:0];
899    
900    reg [1:0] mem [8191:0];
901    
902    reg [8:0] count, countp;
903    reg [1:0] wr_mode_a, wr_mode_b;
904
905    reg [5:0] dmi, dbi;
906    reg [5:0] pmi, pbi;
907
908    wire [12:0] addra_int;
909    reg [12:0] addra_reg;
910    wire [1:0] dia_int;
911    wire ena_int, clka_int, wea_int, ssra_int;
912    reg ena_reg, wea_reg, ssra_reg;
913    wire [12:0] addrb_int;
914    reg [12:0] addrb_reg;
915    wire [1:0] dib_int;
916    wire enb_int, clkb_int, web_int, ssrb_int;
917    reg display_flag, output_flag;
918    reg enb_reg, web_reg, ssrb_reg;
919
920    time time_clka, time_clkb;
921    time time_clka_clkb;
922    time time_clkb_clka;
923
924    reg setup_all_a_b;
925    reg setup_all_b_a;
926    reg setup_zero;
927    reg setup_rf_a_b;
928    reg setup_rf_b_a;
929    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
930    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
931    reg change_clka;
932    reg change_clkb;
933
934    wire [14:0] data_addra_int;
935    wire [14:0] data_addra_reg;
936    wire [14:0] data_addrb_int;
937    wire [14:0] data_addrb_reg;
938
939    wire dia_enable = ena_int && wea_int;
940    wire dib_enable = enb_int && web_int;
941
942    tri0 GSR = glbl.GSR;
943    wire gsr_int;
944
945    buf b_gsr (gsr_int, GSR);
946
947    buf b_doa [1:0] (DOA, doa_out);
948    buf b_addra [12:0] (addra_int, ADDRA);
949    buf b_dia [1:0] (dia_int, DIA);
950    buf b_ena (ena_int, ENA);
951    buf b_clka (clka_int, CLKA);
952    buf b_ssra (ssra_int, SSRA);
953    buf b_wea (wea_int, WEA);
954
955    buf b_dob [1:0] (DOB, dob_out);
956    buf b_addrb [12:0] (addrb_int, ADDRB);
957    buf b_dib [1:0] (dib_int, DIB);
958    buf b_enb (enb_int, ENB);
959    buf b_clkb (clkb_int, CLKB);
960    buf b_ssrb (ssrb_int, SSRB);
961    buf b_web (web_int, WEB);
962
963    
964    always @(gsr_int)
965    if (gsr_int) begin
966        assign {doa_out} = INIT_A;
967        assign {dob_out} = INIT_B;
968    end
969    else begin
970        deassign doa_out;
971        deassign dob_out;
972    end
973
974    
975    initial begin
976
977    for (count = 0; count < 128; count = count + 1) begin
978        mem[count] = INIT_00[(count * 2) +: 2];
979        mem[128 * 1 + count] = INIT_01[(count * 2) +: 2];
980        mem[128 * 2 + count] = INIT_02[(count * 2) +: 2];
981        mem[128 * 3 + count] = INIT_03[(count * 2) +: 2];
982        mem[128 * 4 + count] = INIT_04[(count * 2) +: 2];
983        mem[128 * 5 + count] = INIT_05[(count * 2) +: 2];
984        mem[128 * 6 + count] = INIT_06[(count * 2) +: 2];
985        mem[128 * 7 + count] = INIT_07[(count * 2) +: 2];
986        mem[128 * 8 + count] = INIT_08[(count * 2) +: 2];
987        mem[128 * 9 + count] = INIT_09[(count * 2) +: 2];
988        mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2];
989        mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2];
990        mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2];
991        mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2];
992        mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2];
993        mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2];
994        mem[128 * 16 + count] = INIT_10[(count * 2) +: 2];
995        mem[128 * 17 + count] = INIT_11[(count * 2) +: 2];
996        mem[128 * 18 + count] = INIT_12[(count * 2) +: 2];
997        mem[128 * 19 + count] = INIT_13[(count * 2) +: 2];
998        mem[128 * 20 + count] = INIT_14[(count * 2) +: 2];
999        mem[128 * 21 + count] = INIT_15[(count * 2) +: 2];
1000        mem[128 * 22 + count] = INIT_16[(count * 2) +: 2];
1001        mem[128 * 23 + count] = INIT_17[(count * 2) +: 2];
1002        mem[128 * 24 + count] = INIT_18[(count * 2) +: 2];
1003        mem[128 * 25 + count] = INIT_19[(count * 2) +: 2];
1004        mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2];
1005        mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2];
1006        mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2];
1007        mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2];
1008        mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2];
1009        mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2];
1010        mem[128 * 32 + count] = INIT_20[(count * 2) +: 2];
1011        mem[128 * 33 + count] = INIT_21[(count * 2) +: 2];
1012        mem[128 * 34 + count] = INIT_22[(count * 2) +: 2];
1013        mem[128 * 35 + count] = INIT_23[(count * 2) +: 2];
1014        mem[128 * 36 + count] = INIT_24[(count * 2) +: 2];
1015        mem[128 * 37 + count] = INIT_25[(count * 2) +: 2];
1016        mem[128 * 38 + count] = INIT_26[(count * 2) +: 2];
1017        mem[128 * 39 + count] = INIT_27[(count * 2) +: 2];
1018        mem[128 * 40 + count] = INIT_28[(count * 2) +: 2];
1019        mem[128 * 41 + count] = INIT_29[(count * 2) +: 2];
1020        mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2];
1021        mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2];
1022        mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2];
1023        mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2];
1024        mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2];
1025        mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2];
1026        mem[128 * 48 + count] = INIT_30[(count * 2) +: 2];
1027        mem[128 * 49 + count] = INIT_31[(count * 2) +: 2];
1028        mem[128 * 50 + count] = INIT_32[(count * 2) +: 2];
1029        mem[128 * 51 + count] = INIT_33[(count * 2) +: 2];
1030        mem[128 * 52 + count] = INIT_34[(count * 2) +: 2];
1031        mem[128 * 53 + count] = INIT_35[(count * 2) +: 2];
1032        mem[128 * 54 + count] = INIT_36[(count * 2) +: 2];
1033        mem[128 * 55 + count] = INIT_37[(count * 2) +: 2];
1034        mem[128 * 56 + count] = INIT_38[(count * 2) +: 2];
1035        mem[128 * 57 + count] = INIT_39[(count * 2) +: 2];
1036        mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2];
1037        mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2];
1038        mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2];
1039        mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2];
1040        mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2];
1041        mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2];
1042    end
1043
1044    
1045    change_clka <= 0;
1046    change_clkb <= 0;
1047    data_collision <= 0;
1048    data_collision_a_b <= 0;
1049    data_collision_b_a <= 0;
1050    memory_collision <= 0;
1051    memory_collision_a_b <= 0;
1052    memory_collision_b_a <= 0;
1053    setup_all_a_b <= 0;
1054    setup_all_b_a <= 0;
1055    setup_zero <= 0;
1056    setup_rf_a_b <= 0;
1057    setup_rf_b_a <= 0;
1058    end
1059
1060    assign data_addra_int = addra_int * 2;
1061    assign data_addra_reg = addra_reg * 2;
1062    assign data_addrb_int = addrb_int * 2;
1063    assign data_addrb_reg = addrb_reg * 2;
1064
1065
1066    initial begin
1067
1068    display_flag = 1;
1069    output_flag = 1;
1070    
1071    case (SIM_COLLISION_CHECK)
1072
1073        "NONE" : begin
1074                 output_flag = 0;
1075                     display_flag = 0;
1076                 end
1077        "WARNING_ONLY" : output_flag = 0;
1078        "GENERATE_X_ONLY" : display_flag = 0;
1079        "ALL" : ;
1080
1081        default : begin
1082                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
1083                  $finish;
1084                  end
1085
1086    endcase // case(SIM_COLLISION_CHECK)
1087
1088    end // initial begin
1089
1090    
1091    always @(posedge clka_int) begin
1092    if ((output_flag || display_flag)) begin
1093        time_clka = $time;
1094        #0 time_clkb_clka = time_clka - time_clkb;
1095        change_clka = ~change_clka;
1096    end
1097    end
1098    
1099    always @(posedge clkb_int) begin
1100    if ((output_flag || display_flag)) begin
1101        time_clkb = $time;
1102        #0 time_clka_clkb = time_clkb - time_clka;
1103        change_clkb = ~change_clkb;
1104    end
1105    end
1106    
1107    always @(change_clkb) begin
1108    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
1109        setup_all_a_b = 1;
1110    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
1111        setup_rf_a_b = 1;
1112    end
1113
1114    always @(change_clka) begin
1115    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
1116        setup_all_b_a = 1;
1117    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
1118        setup_rf_b_a = 1;
1119    end
1120
1121    always @(change_clkb or change_clka) begin
1122    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
1123        setup_zero = 1;
1124    end
1125
1126    always @(posedge setup_zero) begin
1127    if ((ena_int == 1) && (wea_int == 1) &&
1128        (enb_int == 1) && (web_int == 1) &&
1129        (data_addra_int[14:1] == data_addrb_int[14:1]))
1130        memory_collision <= 1;
1131    end
1132
1133    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
1134    if ((ena_reg == 1) && (wea_reg == 1) &&
1135        (enb_int == 1) && (web_int == 1) &&
1136        (data_addra_reg[14:1] == data_addrb_int[14:1]))
1137        memory_collision_a_b <= 1;
1138    end
1139
1140    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
1141    if ((ena_int == 1) && (wea_int == 1) &&
1142        (enb_reg == 1) && (web_reg == 1) &&
1143        (data_addra_int[14:1] == data_addrb_reg[14:1]))
1144        memory_collision_b_a <= 1;
1145    end
1146
1147    always @(posedge setup_all_a_b) begin
1148    if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
1149    if ((ena_reg == 1) && (enb_int == 1)) begin
1150        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1151        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1152        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1153        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1154// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1155// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1156// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1157        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1158        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1159        6'b101011 : begin display_wa_wb; end
1160        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1161// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1162        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1163        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1164// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1165        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1166        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1167// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1168        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1169        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1170        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1171        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1172// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1173// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1174// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1175        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1176        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1177        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1178        endcase
1179    end
1180    end
1181    setup_all_a_b <= 0;
1182    end
1183
1184
1185    always @(posedge setup_all_b_a) begin
1186    if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
1187    if ((ena_int == 1) && (enb_reg == 1)) begin
1188        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1189        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1190// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1191        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1192        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1193// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1194        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1195        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1196        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1197        6'b101011 : begin display_wa_wb; end
1198        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1199        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1200        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1201        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1202        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1203        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1204        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1205        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1206        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1207        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1208        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1209        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1210// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1211// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1212// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1213        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1214        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1215        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1216        endcase
1217    end
1218    end
1219    setup_all_b_a <= 0;
1220    end
1221
1222
1223    always @(posedge setup_zero) begin
1224    if (data_addra_int[14:1] == data_addrb_int[14:1]) begin
1225    if ((ena_int == 1) && (enb_int == 1)) begin
1226        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
1227        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
1228        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
1229        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
1230        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
1231        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
1232        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
1233        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
1234        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
1235        6'b101011 : begin display_wa_wb; end
1236        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
1237// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
1238        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
1239        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
1240// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
1241        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
1242        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
1243// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
1244        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
1245        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
1246        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
1247        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
1248// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
1249// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
1250// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
1251        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
1252        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
1253        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
1254        endcase
1255    end
1256    end
1257    setup_zero <= 0;
1258    end
1259
1260    task display_ra_wb;
1261    begin
1262    if (display_flag)
1263        $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
1264    end
1265    endtask
1266
1267    task display_wa_rb;
1268    begin
1269    if (display_flag)
1270        $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
1271    end
1272    endtask
1273
1274    task display_wa_wb;
1275    begin
1276    if (display_flag)
1277        $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
1278    end
1279    endtask
1280
1281
1282    always @(posedge setup_rf_a_b) begin
1283    if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin
1284    if ((ena_reg == 1) && (enb_int == 1)) begin
1285        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1286// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1287// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1288// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1289        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1290        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1291        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1292// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1293// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1294// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1295// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1296// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1297// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1298// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1299// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1300// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1301// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1302// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1303// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1304// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1305// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1306// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1307        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1308        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1309        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1310// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1311// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1312// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1313        endcase
1314    end
1315    end
1316    setup_rf_a_b <= 0;
1317    end
1318
1319
1320    always @(posedge setup_rf_b_a) begin
1321    if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin
1322    if ((ena_int == 1) && (enb_reg == 1)) begin
1323        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1324// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1325        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1326// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1327// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1328        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1329// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1330// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1331        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1332// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1333// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1334        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1335// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1336// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1337        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1338// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1339// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1340        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1341// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1342// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1343// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1344// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1345// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1346// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1347// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1348// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1349// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1350// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1351        endcase
1352    end
1353    end
1354    setup_rf_b_a <= 0;
1355    end
1356
1357
1358    always @(posedge clka_int) begin
1359    if ((output_flag || display_flag)) begin
1360        addra_reg <= addra_int;
1361        ena_reg <= ena_int;
1362        ssra_reg <= ssra_int;
1363        wea_reg <= wea_int;
1364    end
1365    end
1366    
1367    always @(posedge clkb_int) begin
1368    if ((output_flag || display_flag)) begin
1369        addrb_reg <= addrb_int;
1370        enb_reg <= enb_int;
1371        ssrb_reg <= ssrb_int;
1372        web_reg <= web_int;
1373    end
1374    end
1375    
1376        
1377    // Data
1378    always @(posedge memory_collision) begin
1379    if ((output_flag || display_flag)) begin
1380        mem[addra_int] <= 2'bx;
1381        memory_collision <= 0;
1382    end
1383    
1384    end
1385
1386    always @(posedge memory_collision_a_b) begin
1387    if ((output_flag || display_flag)) begin
1388        mem[addra_reg] <= 2'bx;
1389        memory_collision_a_b <= 0;
1390    end
1391    end
1392    
1393    always @(posedge memory_collision_b_a) begin
1394    if ((output_flag || display_flag)) begin
1395        mem[addra_int] <= 2'bx;
1396        memory_collision_b_a <= 0;
1397    end
1398    end
1399    
1400    always @(posedge data_collision[1]) begin
1401    if (ssra_int == 0 && output_flag) begin
1402        doa_out <= #100 2'bX;
1403    end
1404    data_collision[1] <= 0;
1405    end
1406
1407    always @(posedge data_collision[0]) begin
1408    if (ssrb_int == 0 && output_flag) begin
1409        dob_out <= #100 2'bX;
1410    end
1411    data_collision[0] <= 0;
1412    end
1413
1414    always @(posedge data_collision_a_b[1]) begin
1415    if (ssra_reg == 0 && output_flag) begin
1416        doa_out <= #100 2'bX;
1417    end
1418    data_collision_a_b[1] <= 0;
1419    end
1420
1421    always @(posedge data_collision_a_b[0]) begin
1422    if (ssrb_int == 0 && output_flag) begin
1423        dob_out <= #100 2'bX;
1424    end
1425    data_collision_a_b[0] <= 0;
1426    end
1427
1428    always @(posedge data_collision_b_a[1]) begin
1429    if (ssra_int == 0 && output_flag) begin
1430        doa_out <= #100 2'bX;
1431    end
1432    data_collision_b_a[1] <= 0;
1433    end
1434
1435    always @(posedge data_collision_b_a[0]) begin
1436    if (ssrb_reg == 0 && output_flag) begin
1437        dob_out <= #100 2'bX;
1438    end
1439    data_collision_b_a[0] <= 0;
1440    end
1441
1442
1443    initial begin
1444    case (WRITE_MODE_A)
1445        "WRITE_FIRST" : wr_mode_a <= 2'b00;
1446        "READ_FIRST" : wr_mode_a <= 2'b01;
1447        "NO_CHANGE" : wr_mode_a <= 2'b10;
1448        default : begin
1449                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
1450                $finish;
1451                end
1452    endcase
1453    end
1454
1455    initial begin
1456    case (WRITE_MODE_B)
1457        "WRITE_FIRST" : wr_mode_b <= 2'b00;
1458        "READ_FIRST" : wr_mode_b <= 2'b01;
1459        "NO_CHANGE" : wr_mode_b <= 2'b10;
1460        default : begin
1461                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
1462                $finish;
1463                end
1464    endcase
1465    end
1466
1467
1468    // Port A
1469    always @(posedge clka_int) begin
1470
1471    if (ena_int == 1'b1) begin
1472
1473        if (ssra_int == 1'b1) begin
1474        {doa_out} <= #100 SRVAL_A;
1475        end
1476        else begin
1477        if (wea_int == 1'b1) begin
1478            if (wr_mode_a == 2'b00) begin
1479            doa_out <= #100 dia_int;
1480            end
1481            else if (wr_mode_a == 2'b01) begin
1482
1483            doa_out <= #100 mem[addra_int];
1484
1485            end
1486        end
1487        else begin
1488
1489            doa_out <= #100 mem[addra_int];
1490            
1491        end
1492        end
1493
1494        // memory
1495        if (wea_int == 1'b1) begin
1496        mem[addra_int] <= dia_int;
1497        end
1498        
1499    end
1500    end
1501
1502
1503    // Port B
1504    always @(posedge clkb_int) begin
1505
1506    if (enb_int == 1'b1) begin
1507
1508        if (ssrb_int == 1'b1) begin
1509        {dob_out} <= #100 SRVAL_B;
1510        end
1511        else begin
1512        if (web_int == 1'b1) begin
1513            if (wr_mode_b == 2'b00) begin
1514            dob_out <= #100 dib_int;
1515            end
1516            else if (wr_mode_b == 2'b01) begin
1517            dob_out <= #100 mem[addrb_int];
1518            end
1519        end
1520        else begin
1521            dob_out <= #100 mem[addrb_int];
1522        end
1523        end
1524
1525        // memory
1526        if (web_int == 1'b1) begin
1527        mem[addrb_int] <= dib_int;
1528        end
1529
1530    end
1531    end
1532
1533
1534endmodule
1535
1536`endif
1537

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