Root/Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S36.v

1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S36.v,v 1.9.158.2 2007/03/09 18:13:18 patrickp Exp $
2///////////////////////////////////////////////////////////////////////////////
3// Copyright (c) 1995/2005 Xilinx, Inc.
4// All Right Reserved.
5///////////////////////////////////////////////////////////////////////////////
6// ____ ____
7// / /\/ /
8// /___/ \ / Vendor : Xilinx
9// \ \ \/ Version : 8.1i (I.13)
10// \ \ Description : Xilinx Functional Simulation Library Component
11// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
12// /___/ /\ Filename : RAMB16_S2_S36.v
13// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005
14// \___\/\___\
15//
16// Revision:
17// 03/23/04 - Initial version.
18// End Revision
19
20`ifdef legacy_model
21
22`timescale 1 ps / 1 ps
23
24module RAMB16_S2_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
25
26    parameter INIT_A = 2'h0;
27    parameter INIT_B = 36'h0;
28    parameter SRVAL_A = 2'h0;
29    parameter SRVAL_B = 36'h0;
30    parameter WRITE_MODE_A = "WRITE_FIRST";
31    parameter WRITE_MODE_B = "WRITE_FIRST";
32    parameter SIM_COLLISION_CHECK = "ALL";
33    localparam SETUP_ALL = 1000;
34    localparam SETUP_READ_FIRST = 3000;
35
36    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
95    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
96    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
97    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
98    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
99    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
100    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
101    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
102    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
103    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
104    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
105    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
106    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
107    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
108
109    output [1:0] DOA;
110    reg [1:0] doa_out;
111    wire doa_out0, doa_out1;
112
113    input [12:0] ADDRA;
114    input [1:0] DIA;
115    input ENA, CLKA, WEA, SSRA;
116
117    output [31:0] DOB;
118    output [3:0] DOPB;
119    reg [31:0] dob_out;
120    reg [3:0] dopb_out;
121    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31;
122    wire dopb0_out, dopb1_out, dopb2_out, dopb3_out;
123
124    input [8:0] ADDRB;
125    input [31:0] DIB;
126    input [3:0] DIPB;
127    input ENB, CLKB, WEB, SSRB;
128
129    reg [18431:0] mem;
130    reg [8:0] count;
131    reg [1:0] wr_mode_a, wr_mode_b;
132
133    reg [5:0] dmi, dbi;
134    reg [5:0] pmi, pbi;
135
136    wire [12:0] addra_int;
137    reg [12:0] addra_reg;
138    wire [1:0] dia_int;
139    wire ena_int, clka_int, wea_int, ssra_int;
140    reg ena_reg, wea_reg, ssra_reg;
141    wire [8:0] addrb_int;
142    reg [8:0] addrb_reg;
143    wire [31:0] dib_int;
144    wire [3:0] dipb_int;
145    wire enb_int, clkb_int, web_int, ssrb_int;
146    reg display_flag;
147    reg enb_reg, web_reg, ssrb_reg;
148
149    time time_clka, time_clkb;
150    time time_clka_clkb;
151    time time_clkb_clka;
152
153    reg setup_all_a_b;
154    reg setup_all_b_a;
155    reg setup_zero;
156    reg setup_rf_a_b;
157    reg setup_rf_b_a;
158    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
159    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
160    reg address_collision, address_collision_a_b, address_collision_b_a;
161    reg change_clka;
162    reg change_clkb;
163
164    wire [14:0] data_addra_int;
165    wire [14:0] data_addra_reg;
166    wire [14:0] data_addrb_int;
167    wire [14:0] data_addrb_reg;
168    wire [15:0] parity_addra_int;
169    wire [15:0] parity_addra_reg;
170    wire [15:0] parity_addrb_int;
171    wire [15:0] parity_addrb_reg;
172
173    tri0 GSR = glbl.GSR;
174
175    always @(GSR)
176    if (GSR) begin
177        assign doa_out = INIT_A[1:0];
178        assign dob_out = INIT_B[31:0];
179        assign dopb_out = INIT_B[35:32];
180    end
181    else begin
182        deassign doa_out;
183        deassign dob_out;
184        deassign dopb_out;
185    end
186
187    buf b_doa_out0 (doa_out0, doa_out[0]);
188    buf b_doa_out1 (doa_out1, doa_out[1]);
189    buf b_dob_out0 (dob_out0, dob_out[0]);
190    buf b_dob_out1 (dob_out1, dob_out[1]);
191    buf b_dob_out2 (dob_out2, dob_out[2]);
192    buf b_dob_out3 (dob_out3, dob_out[3]);
193    buf b_dob_out4 (dob_out4, dob_out[4]);
194    buf b_dob_out5 (dob_out5, dob_out[5]);
195    buf b_dob_out6 (dob_out6, dob_out[6]);
196    buf b_dob_out7 (dob_out7, dob_out[7]);
197    buf b_dob_out8 (dob_out8, dob_out[8]);
198    buf b_dob_out9 (dob_out9, dob_out[9]);
199    buf b_dob_out10 (dob_out10, dob_out[10]);
200    buf b_dob_out11 (dob_out11, dob_out[11]);
201    buf b_dob_out12 (dob_out12, dob_out[12]);
202    buf b_dob_out13 (dob_out13, dob_out[13]);
203    buf b_dob_out14 (dob_out14, dob_out[14]);
204    buf b_dob_out15 (dob_out15, dob_out[15]);
205    buf b_dob_out16 (dob_out16, dob_out[16]);
206    buf b_dob_out17 (dob_out17, dob_out[17]);
207    buf b_dob_out18 (dob_out18, dob_out[18]);
208    buf b_dob_out19 (dob_out19, dob_out[19]);
209    buf b_dob_out20 (dob_out20, dob_out[20]);
210    buf b_dob_out21 (dob_out21, dob_out[21]);
211    buf b_dob_out22 (dob_out22, dob_out[22]);
212    buf b_dob_out23 (dob_out23, dob_out[23]);
213    buf b_dob_out24 (dob_out24, dob_out[24]);
214    buf b_dob_out25 (dob_out25, dob_out[25]);
215    buf b_dob_out26 (dob_out26, dob_out[26]);
216    buf b_dob_out27 (dob_out27, dob_out[27]);
217    buf b_dob_out28 (dob_out28, dob_out[28]);
218    buf b_dob_out29 (dob_out29, dob_out[29]);
219    buf b_dob_out30 (dob_out30, dob_out[30]);
220    buf b_dob_out31 (dob_out31, dob_out[31]);
221    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
222    buf b_dopb_out1 (dopb_out1, dopb_out[1]);
223    buf b_dopb_out2 (dopb_out2, dopb_out[2]);
224    buf b_dopb_out3 (dopb_out3, dopb_out[3]);
225
226    buf b_doa0 (DOA[0], doa_out0);
227    buf b_doa1 (DOA[1], doa_out1);
228    buf b_dob0 (DOB[0], dob_out0);
229    buf b_dob1 (DOB[1], dob_out1);
230    buf b_dob2 (DOB[2], dob_out2);
231    buf b_dob3 (DOB[3], dob_out3);
232    buf b_dob4 (DOB[4], dob_out4);
233    buf b_dob5 (DOB[5], dob_out5);
234    buf b_dob6 (DOB[6], dob_out6);
235    buf b_dob7 (DOB[7], dob_out7);
236    buf b_dob8 (DOB[8], dob_out8);
237    buf b_dob9 (DOB[9], dob_out9);
238    buf b_dob10 (DOB[10], dob_out10);
239    buf b_dob11 (DOB[11], dob_out11);
240    buf b_dob12 (DOB[12], dob_out12);
241    buf b_dob13 (DOB[13], dob_out13);
242    buf b_dob14 (DOB[14], dob_out14);
243    buf b_dob15 (DOB[15], dob_out15);
244    buf b_dob16 (DOB[16], dob_out16);
245    buf b_dob17 (DOB[17], dob_out17);
246    buf b_dob18 (DOB[18], dob_out18);
247    buf b_dob19 (DOB[19], dob_out19);
248    buf b_dob20 (DOB[20], dob_out20);
249    buf b_dob21 (DOB[21], dob_out21);
250    buf b_dob22 (DOB[22], dob_out22);
251    buf b_dob23 (DOB[23], dob_out23);
252    buf b_dob24 (DOB[24], dob_out24);
253    buf b_dob25 (DOB[25], dob_out25);
254    buf b_dob26 (DOB[26], dob_out26);
255    buf b_dob27 (DOB[27], dob_out27);
256    buf b_dob28 (DOB[28], dob_out28);
257    buf b_dob29 (DOB[29], dob_out29);
258    buf b_dob30 (DOB[30], dob_out30);
259    buf b_dob31 (DOB[31], dob_out31);
260    buf b_dopb0 (DOPB[0], dopb_out0);
261    buf b_dopb1 (DOPB[1], dopb_out1);
262    buf b_dopb2 (DOPB[2], dopb_out2);
263    buf b_dopb3 (DOPB[3], dopb_out3);
264
265    buf b_addra_0 (addra_int[0], ADDRA[0]);
266    buf b_addra_1 (addra_int[1], ADDRA[1]);
267    buf b_addra_2 (addra_int[2], ADDRA[2]);
268    buf b_addra_3 (addra_int[3], ADDRA[3]);
269    buf b_addra_4 (addra_int[4], ADDRA[4]);
270    buf b_addra_5 (addra_int[5], ADDRA[5]);
271    buf b_addra_6 (addra_int[6], ADDRA[6]);
272    buf b_addra_7 (addra_int[7], ADDRA[7]);
273    buf b_addra_8 (addra_int[8], ADDRA[8]);
274    buf b_addra_9 (addra_int[9], ADDRA[9]);
275    buf b_addra_10 (addra_int[10], ADDRA[10]);
276    buf b_addra_11 (addra_int[11], ADDRA[11]);
277    buf b_addra_12 (addra_int[12], ADDRA[12]);
278    buf b_dia_0 (dia_int[0], DIA[0]);
279    buf b_dia_1 (dia_int[1], DIA[1]);
280    buf b_ena (ena_int, ENA);
281    buf b_clka (clka_int, CLKA);
282    buf b_ssra (ssra_int, SSRA);
283    buf b_wea (wea_int, WEA);
284    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
285    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
286    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
287    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
288    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
289    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
290    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
291    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
292    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
293    buf b_dib_0 (dib_int[0], DIB[0]);
294    buf b_dib_1 (dib_int[1], DIB[1]);
295    buf b_dib_2 (dib_int[2], DIB[2]);
296    buf b_dib_3 (dib_int[3], DIB[3]);
297    buf b_dib_4 (dib_int[4], DIB[4]);
298    buf b_dib_5 (dib_int[5], DIB[5]);
299    buf b_dib_6 (dib_int[6], DIB[6]);
300    buf b_dib_7 (dib_int[7], DIB[7]);
301    buf b_dib_8 (dib_int[8], DIB[8]);
302    buf b_dib_9 (dib_int[9], DIB[9]);
303    buf b_dib_10 (dib_int[10], DIB[10]);
304    buf b_dib_11 (dib_int[11], DIB[11]);
305    buf b_dib_12 (dib_int[12], DIB[12]);
306    buf b_dib_13 (dib_int[13], DIB[13]);
307    buf b_dib_14 (dib_int[14], DIB[14]);
308    buf b_dib_15 (dib_int[15], DIB[15]);
309    buf b_dib_16 (dib_int[16], DIB[16]);
310    buf b_dib_17 (dib_int[17], DIB[17]);
311    buf b_dib_18 (dib_int[18], DIB[18]);
312    buf b_dib_19 (dib_int[19], DIB[19]);
313    buf b_dib_20 (dib_int[20], DIB[20]);
314    buf b_dib_21 (dib_int[21], DIB[21]);
315    buf b_dib_22 (dib_int[22], DIB[22]);
316    buf b_dib_23 (dib_int[23], DIB[23]);
317    buf b_dib_24 (dib_int[24], DIB[24]);
318    buf b_dib_25 (dib_int[25], DIB[25]);
319    buf b_dib_26 (dib_int[26], DIB[26]);
320    buf b_dib_27 (dib_int[27], DIB[27]);
321    buf b_dib_28 (dib_int[28], DIB[28]);
322    buf b_dib_29 (dib_int[29], DIB[29]);
323    buf b_dib_30 (dib_int[30], DIB[30]);
324    buf b_dib_31 (dib_int[31], DIB[31]);
325    buf b_dipb_0 (dipb_int[0], DIPB[0]);
326    buf b_dipb_1 (dipb_int[1], DIPB[1]);
327    buf b_dipb_2 (dipb_int[2], DIPB[2]);
328    buf b_dipb_3 (dipb_int[3], DIPB[3]);
329    buf b_enb (enb_int, ENB);
330    buf b_clkb (clkb_int, CLKB);
331    buf b_ssrb (ssrb_int, SSRB);
332    buf b_web (web_int, WEB);
333
334    initial begin
335    for (count = 0; count < 256; count = count + 1) begin
336        mem[count] <= INIT_00[count];
337        mem[256 * 1 + count] <= INIT_01[count];
338        mem[256 * 2 + count] <= INIT_02[count];
339        mem[256 * 3 + count] <= INIT_03[count];
340        mem[256 * 4 + count] <= INIT_04[count];
341        mem[256 * 5 + count] <= INIT_05[count];
342        mem[256 * 6 + count] <= INIT_06[count];
343        mem[256 * 7 + count] <= INIT_07[count];
344        mem[256 * 8 + count] <= INIT_08[count];
345        mem[256 * 9 + count] <= INIT_09[count];
346        mem[256 * 10 + count] <= INIT_0A[count];
347        mem[256 * 11 + count] <= INIT_0B[count];
348        mem[256 * 12 + count] <= INIT_0C[count];
349        mem[256 * 13 + count] <= INIT_0D[count];
350        mem[256 * 14 + count] <= INIT_0E[count];
351        mem[256 * 15 + count] <= INIT_0F[count];
352        mem[256 * 16 + count] <= INIT_10[count];
353        mem[256 * 17 + count] <= INIT_11[count];
354        mem[256 * 18 + count] <= INIT_12[count];
355        mem[256 * 19 + count] <= INIT_13[count];
356        mem[256 * 20 + count] <= INIT_14[count];
357        mem[256 * 21 + count] <= INIT_15[count];
358        mem[256 * 22 + count] <= INIT_16[count];
359        mem[256 * 23 + count] <= INIT_17[count];
360        mem[256 * 24 + count] <= INIT_18[count];
361        mem[256 * 25 + count] <= INIT_19[count];
362        mem[256 * 26 + count] <= INIT_1A[count];
363        mem[256 * 27 + count] <= INIT_1B[count];
364        mem[256 * 28 + count] <= INIT_1C[count];
365        mem[256 * 29 + count] <= INIT_1D[count];
366        mem[256 * 30 + count] <= INIT_1E[count];
367        mem[256 * 31 + count] <= INIT_1F[count];
368        mem[256 * 32 + count] <= INIT_20[count];
369        mem[256 * 33 + count] <= INIT_21[count];
370        mem[256 * 34 + count] <= INIT_22[count];
371        mem[256 * 35 + count] <= INIT_23[count];
372        mem[256 * 36 + count] <= INIT_24[count];
373        mem[256 * 37 + count] <= INIT_25[count];
374        mem[256 * 38 + count] <= INIT_26[count];
375        mem[256 * 39 + count] <= INIT_27[count];
376        mem[256 * 40 + count] <= INIT_28[count];
377        mem[256 * 41 + count] <= INIT_29[count];
378        mem[256 * 42 + count] <= INIT_2A[count];
379        mem[256 * 43 + count] <= INIT_2B[count];
380        mem[256 * 44 + count] <= INIT_2C[count];
381        mem[256 * 45 + count] <= INIT_2D[count];
382        mem[256 * 46 + count] <= INIT_2E[count];
383        mem[256 * 47 + count] <= INIT_2F[count];
384        mem[256 * 48 + count] <= INIT_30[count];
385        mem[256 * 49 + count] <= INIT_31[count];
386        mem[256 * 50 + count] <= INIT_32[count];
387        mem[256 * 51 + count] <= INIT_33[count];
388        mem[256 * 52 + count] <= INIT_34[count];
389        mem[256 * 53 + count] <= INIT_35[count];
390        mem[256 * 54 + count] <= INIT_36[count];
391        mem[256 * 55 + count] <= INIT_37[count];
392        mem[256 * 56 + count] <= INIT_38[count];
393        mem[256 * 57 + count] <= INIT_39[count];
394        mem[256 * 58 + count] <= INIT_3A[count];
395        mem[256 * 59 + count] <= INIT_3B[count];
396        mem[256 * 60 + count] <= INIT_3C[count];
397        mem[256 * 61 + count] <= INIT_3D[count];
398        mem[256 * 62 + count] <= INIT_3E[count];
399        mem[256 * 63 + count] <= INIT_3F[count];
400        mem[256 * 64 + count] <= INITP_00[count];
401        mem[256 * 65 + count] <= INITP_01[count];
402        mem[256 * 66 + count] <= INITP_02[count];
403        mem[256 * 67 + count] <= INITP_03[count];
404        mem[256 * 68 + count] <= INITP_04[count];
405        mem[256 * 69 + count] <= INITP_05[count];
406        mem[256 * 70 + count] <= INITP_06[count];
407        mem[256 * 71 + count] <= INITP_07[count];
408    end
409    address_collision <= 0;
410    address_collision_a_b <= 0;
411    address_collision_b_a <= 0;
412    change_clka <= 0;
413    change_clkb <= 0;
414    data_collision <= 0;
415    data_collision_a_b <= 0;
416    data_collision_b_a <= 0;
417    memory_collision <= 0;
418    memory_collision_a_b <= 0;
419    memory_collision_b_a <= 0;
420    setup_all_a_b <= 0;
421    setup_all_b_a <= 0;
422    setup_zero <= 0;
423    setup_rf_a_b <= 0;
424    setup_rf_b_a <= 0;
425    end
426
427    assign data_addra_int = addra_int * 2;
428    assign data_addra_reg = addra_reg * 2;
429    assign data_addrb_int = addrb_int * 32;
430    assign data_addrb_reg = addrb_reg * 32;
431    assign parity_addrb_int = 16384 + addrb_int * 4;
432    assign parity_addrb_reg = 16384 + addrb_reg * 4;
433
434
435    initial begin
436
437    display_flag = 1;
438
439    case (SIM_COLLISION_CHECK)
440
441        "NONE" : begin
442                 assign setup_all_a_b = 1'b0;
443                     assign setup_all_b_a = 1'b0;
444                     assign setup_zero = 1'b0;
445                     assign setup_rf_a_b = 1'b0;
446                     assign setup_rf_b_a = 1'b0;
447                     assign display_flag = 0;
448                 end
449        "WARNING_ONLY" : begin
450                         assign data_collision = 2'b00;
451                             assign data_collision_a_b = 2'b00;
452                             assign data_collision_b_a = 2'b00;
453                             assign memory_collision = 1'b0;
454                             assign memory_collision_a_b = 1'b0;
455                             assign memory_collision_b_a = 1'b0;
456                         end
457        "GENERATE_X_ONLY" : begin
458                            assign display_flag = 0;
459                            end
460        "ALL" : ;
461        default : begin
462                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
463                  $finish;
464                  end
465
466    endcase // case(SIM_COLLISION_CHECK)
467
468    end // initial begin
469
470
471    always @(posedge clka_int) begin
472    time_clka = $time;
473    #0 time_clkb_clka = time_clka - time_clkb;
474    change_clka = ~change_clka;
475    end
476
477    always @(posedge clkb_int) begin
478    time_clkb = $time;
479    #0 time_clka_clkb = time_clkb - time_clka;
480    change_clkb = ~change_clkb;
481    end
482
483    always @(change_clkb) begin
484    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
485        setup_all_a_b = 1;
486    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
487        setup_rf_a_b = 1;
488    end
489
490    always @(change_clka) begin
491    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
492        setup_all_b_a = 1;
493    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
494        setup_rf_b_a = 1;
495    end
496
497    always @(change_clkb or change_clka) begin
498    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
499        setup_zero = 1;
500    end
501
502    always @(posedge setup_zero) begin
503    if ((ena_int == 1) && (wea_int == 1) &&
504        (enb_int == 1) && (web_int == 1) &&
505        (data_addra_int[14:5] == data_addrb_int[14:5]))
506        memory_collision <= 1;
507    end
508
509    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
510    if ((ena_reg == 1) && (wea_reg == 1) &&
511        (enb_int == 1) && (web_int == 1) &&
512        (data_addra_reg[14:5] == data_addrb_int[14:5]))
513        memory_collision_a_b <= 1;
514    end
515
516    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
517    if ((ena_int == 1) && (wea_int == 1) &&
518        (enb_reg == 1) && (web_reg == 1) &&
519        (data_addra_int[14:5] == data_addrb_reg[14:5]))
520        memory_collision_b_a <= 1;
521    end
522
523    always @(posedge setup_all_a_b) begin
524    if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
525    if ((ena_reg == 1) && (enb_int == 1)) begin
526        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
527        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
528        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
529        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
530// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
531// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
532// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
533        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
534        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
535        6'b101011 : begin display_wa_wb; end
536        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
537// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
538        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
539        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
540// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
541        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
542        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
543// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
544        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
545        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
546        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
547        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
548// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
549// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
550// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
551        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
552        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
553        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
554        endcase
555    end
556    end
557    setup_all_a_b <= 0;
558    end
559
560
561    always @(posedge setup_all_b_a) begin
562    if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
563    if ((ena_int == 1) && (enb_reg == 1)) begin
564        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
565        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
566// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
567        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
568        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
569// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
570        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
571        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
572        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
573        6'b101011 : begin display_wa_wb; end
574        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
575        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
576        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
577        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
578        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
579        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
580        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
581        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
582        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
583        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
584        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
585        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
586// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
587// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
588// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
589        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
590        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
591        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
592        endcase
593    end
594    end
595    setup_all_b_a <= 0;
596    end
597
598
599    always @(posedge setup_zero) begin
600    if (data_addra_int[14:5] == data_addrb_int[14:5]) begin
601    if ((ena_int == 1) && (enb_int == 1)) begin
602        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
603        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
604        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
605        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
606        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
607        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
608        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
609        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
610        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
611        6'b101011 : begin display_wa_wb; end
612        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
613// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
614        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
615        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
616// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
617        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
618        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
619// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
620        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
621        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
622        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
623        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
624// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
625// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
626// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
627        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
628        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
629        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
630        endcase
631    end
632    end
633    setup_zero <= 0;
634    end
635
636    task display_ra_wb;
637    begin
638    if (display_flag)
639        $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
640    end
641    endtask
642
643    task display_wa_rb;
644    begin
645    if (display_flag)
646        $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
647    end
648    endtask
649
650    task display_wa_wb;
651    begin
652    if (display_flag)
653        $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
654    end
655    endtask
656
657
658    always @(posedge setup_rf_a_b) begin
659    if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
660    if ((ena_reg == 1) && (enb_int == 1)) begin
661        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
662// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
663// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
664// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
665        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
666        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
667        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
668// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
669// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
670// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
671// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
672// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
673// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
674// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
675// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
676// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
677// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
678// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
679// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
680// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
681// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
682// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
683        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
684        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
685        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
686// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
687// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
688// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
689        endcase
690    end
691    end
692    setup_rf_a_b <= 0;
693    end
694
695
696    always @(posedge setup_rf_b_a) begin
697    if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
698    if ((ena_int == 1) && (enb_reg == 1)) begin
699        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
700// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
701        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
702// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
703// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
704        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
705// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
706// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
707        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
708// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
709// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
710        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
711// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
712// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
713        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
714// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
715// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
716        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
717// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
718// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
719// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
720// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
721// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
722// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
723// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
724// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
725// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
726// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
727        endcase
728    end
729    end
730    setup_rf_b_a <= 0;
731    end
732
733
734    always @(posedge clka_int) begin
735    addra_reg <= addra_int;
736    ena_reg <= ena_int;
737    ssra_reg <= ssra_int;
738    wea_reg <= wea_int;
739    end
740
741    always @(posedge clkb_int) begin
742    addrb_reg <= addrb_int;
743    enb_reg <= enb_int;
744    ssrb_reg <= ssrb_int;
745    web_reg <= web_int;
746    end
747
748    // Data
749    always @(posedge memory_collision) begin
750    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
751        mem[data_addra_int + dmi] <= 1'bX;
752    end
753    memory_collision <= 0;
754    end
755
756    always @(posedge memory_collision_a_b) begin
757    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
758        mem[data_addra_reg + dmi] <= 1'bX;
759    end
760    memory_collision_a_b <= 0;
761    end
762
763    always @(posedge memory_collision_b_a) begin
764    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
765        mem[data_addra_int + dmi] <= 1'bX;
766    end
767    memory_collision_b_a <= 0;
768    end
769
770    always @(posedge data_collision[1]) begin
771    if (ssra_int == 0) begin
772        doa_out <= 2'bX;
773    end
774    data_collision[1] <= 0;
775    end
776
777    always @(posedge data_collision[0]) begin
778    if (ssrb_int == 0) begin
779        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
780        dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX;
781        end
782    end
783    data_collision[0] <= 0;
784    end
785
786    always @(posedge data_collision_a_b[1]) begin
787    if (ssra_reg == 0) begin
788        doa_out <= 2'bX;
789    end
790    data_collision_a_b[1] <= 0;
791    end
792
793    always @(posedge data_collision_a_b[0]) begin
794    if (ssrb_int == 0) begin
795        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
796        dob_out[data_addra_reg[4 : 0] + dbi] <= 1'bX;
797        end
798    end
799    data_collision_a_b[0] <= 0;
800    end
801
802    always @(posedge data_collision_b_a[1]) begin
803    if (ssra_int == 0) begin
804        doa_out <= 2'bX;
805    end
806    data_collision_b_a[1] <= 0;
807    end
808
809    always @(posedge data_collision_b_a[0]) begin
810    if (ssrb_reg == 0) begin
811        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
812        dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX;
813        end
814    end
815    data_collision_b_a[0] <= 0;
816    end
817
818
819    initial begin
820    case (WRITE_MODE_A)
821        "WRITE_FIRST" : wr_mode_a <= 2'b00;
822        "READ_FIRST" : wr_mode_a <= 2'b01;
823        "NO_CHANGE" : wr_mode_a <= 2'b10;
824        default : begin
825                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
826                $finish;
827                end
828    endcase
829    end
830
831    initial begin
832    case (WRITE_MODE_B)
833        "WRITE_FIRST" : wr_mode_b <= 2'b00;
834        "READ_FIRST" : wr_mode_b <= 2'b01;
835        "NO_CHANGE" : wr_mode_b <= 2'b10;
836        default : begin
837                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
838                $finish;
839                end
840    endcase
841    end
842
843    // Port A
844    always @(posedge clka_int) begin
845    if (ena_int == 1'b1) begin
846        if (ssra_int == 1'b1) begin
847        doa_out[0] <= SRVAL_A[0];
848        doa_out[1] <= SRVAL_A[1];
849        end
850        else begin
851        if (wea_int == 1'b1) begin
852            if (wr_mode_a == 2'b00) begin
853            doa_out <= dia_int;
854            end
855            else if (wr_mode_a == 2'b01) begin
856            doa_out[0] <= mem[data_addra_int + 0];
857            doa_out[1] <= mem[data_addra_int + 1];
858            end
859        end
860        else begin
861            doa_out[0] <= mem[data_addra_int + 0];
862            doa_out[1] <= mem[data_addra_int + 1];
863        end
864        end
865    end
866    end
867
868    always @(posedge clka_int) begin
869    if (ena_int == 1'b1 && wea_int == 1'b1) begin
870        mem[data_addra_int + 0] <= dia_int[0];
871        mem[data_addra_int + 1] <= dia_int[1];
872    end
873    end
874
875    // Port B
876    always @(posedge clkb_int) begin
877    if (enb_int == 1'b1) begin
878        if (ssrb_int == 1'b1) begin
879        dob_out[0] <= SRVAL_B[0];
880        dob_out[1] <= SRVAL_B[1];
881        dob_out[2] <= SRVAL_B[2];
882        dob_out[3] <= SRVAL_B[3];
883        dob_out[4] <= SRVAL_B[4];
884        dob_out[5] <= SRVAL_B[5];
885        dob_out[6] <= SRVAL_B[6];
886        dob_out[7] <= SRVAL_B[7];
887        dob_out[8] <= SRVAL_B[8];
888        dob_out[9] <= SRVAL_B[9];
889        dob_out[10] <= SRVAL_B[10];
890        dob_out[11] <= SRVAL_B[11];
891        dob_out[12] <= SRVAL_B[12];
892        dob_out[13] <= SRVAL_B[13];
893        dob_out[14] <= SRVAL_B[14];
894        dob_out[15] <= SRVAL_B[15];
895        dob_out[16] <= SRVAL_B[16];
896        dob_out[17] <= SRVAL_B[17];
897        dob_out[18] <= SRVAL_B[18];
898        dob_out[19] <= SRVAL_B[19];
899        dob_out[20] <= SRVAL_B[20];
900        dob_out[21] <= SRVAL_B[21];
901        dob_out[22] <= SRVAL_B[22];
902        dob_out[23] <= SRVAL_B[23];
903        dob_out[24] <= SRVAL_B[24];
904        dob_out[25] <= SRVAL_B[25];
905        dob_out[26] <= SRVAL_B[26];
906        dob_out[27] <= SRVAL_B[27];
907        dob_out[28] <= SRVAL_B[28];
908        dob_out[29] <= SRVAL_B[29];
909        dob_out[30] <= SRVAL_B[30];
910        dob_out[31] <= SRVAL_B[31];
911        dopb_out[0] <= SRVAL_B[32];
912        dopb_out[1] <= SRVAL_B[33];
913        dopb_out[2] <= SRVAL_B[34];
914        dopb_out[3] <= SRVAL_B[35];
915        end
916        else begin
917        if (web_int == 1'b1) begin
918            if (wr_mode_b == 2'b00) begin
919            dob_out <= dib_int;
920            dopb_out <= dipb_int;
921            end
922            else if (wr_mode_b == 2'b01) begin
923            dob_out[0] <= mem[data_addrb_int + 0];
924            dob_out[1] <= mem[data_addrb_int + 1];
925            dob_out[2] <= mem[data_addrb_int + 2];
926            dob_out[3] <= mem[data_addrb_int + 3];
927            dob_out[4] <= mem[data_addrb_int + 4];
928            dob_out[5] <= mem[data_addrb_int + 5];
929            dob_out[6] <= mem[data_addrb_int + 6];
930            dob_out[7] <= mem[data_addrb_int + 7];
931            dob_out[8] <= mem[data_addrb_int + 8];
932            dob_out[9] <= mem[data_addrb_int + 9];
933            dob_out[10] <= mem[data_addrb_int + 10];
934            dob_out[11] <= mem[data_addrb_int + 11];
935            dob_out[12] <= mem[data_addrb_int + 12];
936            dob_out[13] <= mem[data_addrb_int + 13];
937            dob_out[14] <= mem[data_addrb_int + 14];
938            dob_out[15] <= mem[data_addrb_int + 15];
939            dob_out[16] <= mem[data_addrb_int + 16];
940            dob_out[17] <= mem[data_addrb_int + 17];
941            dob_out[18] <= mem[data_addrb_int + 18];
942            dob_out[19] <= mem[data_addrb_int + 19];
943            dob_out[20] <= mem[data_addrb_int + 20];
944            dob_out[21] <= mem[data_addrb_int + 21];
945            dob_out[22] <= mem[data_addrb_int + 22];
946            dob_out[23] <= mem[data_addrb_int + 23];
947            dob_out[24] <= mem[data_addrb_int + 24];
948            dob_out[25] <= mem[data_addrb_int + 25];
949            dob_out[26] <= mem[data_addrb_int + 26];
950            dob_out[27] <= mem[data_addrb_int + 27];
951            dob_out[28] <= mem[data_addrb_int + 28];
952            dob_out[29] <= mem[data_addrb_int + 29];
953            dob_out[30] <= mem[data_addrb_int + 30];
954            dob_out[31] <= mem[data_addrb_int + 31];
955            dopb_out[0] <= mem[parity_addrb_int + 0];
956            dopb_out[1] <= mem[parity_addrb_int + 1];
957            dopb_out[2] <= mem[parity_addrb_int + 2];
958            dopb_out[3] <= mem[parity_addrb_int + 3];
959            end
960        end
961        else begin
962            dob_out[0] <= mem[data_addrb_int + 0];
963            dob_out[1] <= mem[data_addrb_int + 1];
964            dob_out[2] <= mem[data_addrb_int + 2];
965            dob_out[3] <= mem[data_addrb_int + 3];
966            dob_out[4] <= mem[data_addrb_int + 4];
967            dob_out[5] <= mem[data_addrb_int + 5];
968            dob_out[6] <= mem[data_addrb_int + 6];
969            dob_out[7] <= mem[data_addrb_int + 7];
970            dob_out[8] <= mem[data_addrb_int + 8];
971            dob_out[9] <= mem[data_addrb_int + 9];
972            dob_out[10] <= mem[data_addrb_int + 10];
973            dob_out[11] <= mem[data_addrb_int + 11];
974            dob_out[12] <= mem[data_addrb_int + 12];
975            dob_out[13] <= mem[data_addrb_int + 13];
976            dob_out[14] <= mem[data_addrb_int + 14];
977            dob_out[15] <= mem[data_addrb_int + 15];
978            dob_out[16] <= mem[data_addrb_int + 16];
979            dob_out[17] <= mem[data_addrb_int + 17];
980            dob_out[18] <= mem[data_addrb_int + 18];
981            dob_out[19] <= mem[data_addrb_int + 19];
982            dob_out[20] <= mem[data_addrb_int + 20];
983            dob_out[21] <= mem[data_addrb_int + 21];
984            dob_out[22] <= mem[data_addrb_int + 22];
985            dob_out[23] <= mem[data_addrb_int + 23];
986            dob_out[24] <= mem[data_addrb_int + 24];
987            dob_out[25] <= mem[data_addrb_int + 25];
988            dob_out[26] <= mem[data_addrb_int + 26];
989            dob_out[27] <= mem[data_addrb_int + 27];
990            dob_out[28] <= mem[data_addrb_int + 28];
991            dob_out[29] <= mem[data_addrb_int + 29];
992            dob_out[30] <= mem[data_addrb_int + 30];
993            dob_out[31] <= mem[data_addrb_int + 31];
994            dopb_out[0] <= mem[parity_addrb_int + 0];
995            dopb_out[1] <= mem[parity_addrb_int + 1];
996            dopb_out[2] <= mem[parity_addrb_int + 2];
997            dopb_out[3] <= mem[parity_addrb_int + 3];
998        end
999        end
1000    end
1001    end
1002
1003    always @(posedge clkb_int) begin
1004    if (enb_int == 1'b1 && web_int == 1'b1) begin
1005        mem[data_addrb_int + 0] <= dib_int[0];
1006        mem[data_addrb_int + 1] <= dib_int[1];
1007        mem[data_addrb_int + 2] <= dib_int[2];
1008        mem[data_addrb_int + 3] <= dib_int[3];
1009        mem[data_addrb_int + 4] <= dib_int[4];
1010        mem[data_addrb_int + 5] <= dib_int[5];
1011        mem[data_addrb_int + 6] <= dib_int[6];
1012        mem[data_addrb_int + 7] <= dib_int[7];
1013        mem[data_addrb_int + 8] <= dib_int[8];
1014        mem[data_addrb_int + 9] <= dib_int[9];
1015        mem[data_addrb_int + 10] <= dib_int[10];
1016        mem[data_addrb_int + 11] <= dib_int[11];
1017        mem[data_addrb_int + 12] <= dib_int[12];
1018        mem[data_addrb_int + 13] <= dib_int[13];
1019        mem[data_addrb_int + 14] <= dib_int[14];
1020        mem[data_addrb_int + 15] <= dib_int[15];
1021        mem[data_addrb_int + 16] <= dib_int[16];
1022        mem[data_addrb_int + 17] <= dib_int[17];
1023        mem[data_addrb_int + 18] <= dib_int[18];
1024        mem[data_addrb_int + 19] <= dib_int[19];
1025        mem[data_addrb_int + 20] <= dib_int[20];
1026        mem[data_addrb_int + 21] <= dib_int[21];
1027        mem[data_addrb_int + 22] <= dib_int[22];
1028        mem[data_addrb_int + 23] <= dib_int[23];
1029        mem[data_addrb_int + 24] <= dib_int[24];
1030        mem[data_addrb_int + 25] <= dib_int[25];
1031        mem[data_addrb_int + 26] <= dib_int[26];
1032        mem[data_addrb_int + 27] <= dib_int[27];
1033        mem[data_addrb_int + 28] <= dib_int[28];
1034        mem[data_addrb_int + 29] <= dib_int[29];
1035        mem[data_addrb_int + 30] <= dib_int[30];
1036        mem[data_addrb_int + 31] <= dib_int[31];
1037        mem[parity_addrb_int + 0] <= dipb_int[0];
1038        mem[parity_addrb_int + 1] <= dipb_int[1];
1039        mem[parity_addrb_int + 2] <= dipb_int[2];
1040        mem[parity_addrb_int + 3] <= dipb_int[3];
1041    end
1042    end
1043
1044    specify
1045    (CLKA *> DOA) = (100, 100);
1046    (CLKB *> DOB) = (100, 100);
1047    (CLKB *> DOPB) = (100, 100);
1048    endspecify
1049
1050endmodule
1051
1052`else
1053
1054// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S36.v,v 1.9.158.2 2007/03/09 18:13:18 patrickp Exp $
1055///////////////////////////////////////////////////////////////////////////////
1056// Copyright (c) 1995/2005 Xilinx, Inc.
1057// All Right Reserved.
1058///////////////////////////////////////////////////////////////////////////////
1059// ____ ____
1060// / /\/ /
1061// /___/ \ / Vendor : Xilinx
1062// \ \ \/ Version : 8.1i (I.13)
1063// \ \ Description : Xilinx Timing Simulation Library Component
1064// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
1065// /___/ /\ Filename : RAMB16_S2_S36.v
1066// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
1067// \___\/\___\
1068//
1069// Revision:
1070// 03/23/04 - Initial version.
1071// 03/10/05 - Initialized outputs.
1072// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281).
1073// End Revision
1074
1075`timescale 1 ps/1 ps
1076
1077module RAMB16_S2_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
1078
1079    parameter INIT_A = 2'h0;
1080    parameter INIT_B = 36'h0;
1081    parameter SRVAL_A = 2'h0;
1082    parameter SRVAL_B = 36'h0;
1083    parameter WRITE_MODE_A = "WRITE_FIRST";
1084    parameter WRITE_MODE_B = "WRITE_FIRST";
1085    parameter SIM_COLLISION_CHECK = "ALL";
1086    localparam SETUP_ALL = 1000;
1087    localparam SETUP_READ_FIRST = 3000;
1088
1089    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1090    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1091    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1092    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1093    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1094    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1095    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1096    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1097    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1098    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1099    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1100    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1101    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1102    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1103    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1104    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1105    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1106    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1107    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1108    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1109    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1110    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1111    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1112    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1113    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1114    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1115    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1116    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1117    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1118    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1119    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1120    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1121    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1122    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1123    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1124    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1125    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1126    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1127    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1128    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1129    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1130    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1131    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1132    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1133    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1134    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1135    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1136    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1137    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1138    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1139    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1140    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1141    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1142    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1143    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1144    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1145    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1146    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1147    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1148    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1149    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1150    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1151    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1152    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1153    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1154    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1155    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1156    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1157    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1158    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1159    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1160    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1161
1162    output [1:0] DOA;
1163    output [31:0] DOB;
1164    output [3:0] DOPB;
1165
1166    input [12:0] ADDRA;
1167    input [1:0] DIA;
1168    input ENA, CLKA, WEA, SSRA;
1169    input [8:0] ADDRB;
1170    input [31:0] DIB;
1171    input [3:0] DIPB;
1172    input ENB, CLKB, WEB, SSRB;
1173
1174    reg [1:0] doa_out = INIT_A[1:0];
1175    reg [31:0] dob_out = INIT_B[31:0];
1176    reg [3:0] dopb_out = INIT_B[35:32];
1177    
1178    reg [31:0] mem [511:0];
1179    reg [3:0] memp [511:0];
1180    
1181    reg [8:0] count, countp;
1182    reg [1:0] wr_mode_a, wr_mode_b;
1183
1184    reg [5:0] dmi, dbi;
1185    reg [5:0] pmi, pbi;
1186
1187    wire [12:0] addra_int;
1188    reg [12:0] addra_reg;
1189    wire [1:0] dia_int;
1190    wire ena_int, clka_int, wea_int, ssra_int;
1191    reg ena_reg, wea_reg, ssra_reg;
1192    wire [8:0] addrb_int;
1193    reg [8:0] addrb_reg;
1194    wire [31:0] dib_int;
1195    wire [3:0] dipb_int;
1196    wire enb_int, clkb_int, web_int, ssrb_int;
1197    reg display_flag, output_flag;
1198    reg enb_reg, web_reg, ssrb_reg;
1199
1200    time time_clka, time_clkb;
1201    time time_clka_clkb;
1202    time time_clkb_clka;
1203
1204    reg setup_all_a_b;
1205    reg setup_all_b_a;
1206    reg setup_zero;
1207    reg setup_rf_a_b;
1208    reg setup_rf_b_a;
1209    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
1210    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
1211    reg change_clka;
1212    reg change_clkb;
1213
1214    wire [14:0] data_addra_int;
1215    wire [14:0] data_addra_reg;
1216    wire [14:0] data_addrb_int;
1217    wire [14:0] data_addrb_reg;
1218
1219    wire dia_enable = ena_int && wea_int;
1220    wire dib_enable = enb_int && web_int;
1221
1222    tri0 GSR = glbl.GSR;
1223    wire gsr_int;
1224
1225    buf b_gsr (gsr_int, GSR);
1226
1227    buf b_doa [1:0] (DOA, doa_out);
1228    buf b_addra [12:0] (addra_int, ADDRA);
1229    buf b_dia [1:0] (dia_int, DIA);
1230    buf b_ena (ena_int, ENA);
1231    buf b_clka (clka_int, CLKA);
1232    buf b_ssra (ssra_int, SSRA);
1233    buf b_wea (wea_int, WEA);
1234
1235    buf b_dob [31:0] (DOB, dob_out);
1236    buf b_dopb [3:0] (DOPB, dopb_out);
1237    buf b_addrb [8:0] (addrb_int, ADDRB);
1238    buf b_dib [31:0] (dib_int, DIB);
1239    buf b_dipb [3:0] (dipb_int, DIPB);
1240    buf b_enb (enb_int, ENB);
1241    buf b_clkb (clkb_int, CLKB);
1242    buf b_ssrb (ssrb_int, SSRB);
1243    buf b_web (web_int, WEB);
1244
1245    
1246    always @(gsr_int)
1247    if (gsr_int) begin
1248        assign {doa_out} = INIT_A;
1249        assign {dopb_out, dob_out} = INIT_B;
1250    end
1251    else begin
1252        deassign doa_out;
1253        deassign dob_out;
1254        deassign dopb_out;
1255    end
1256
1257    
1258    initial begin
1259
1260    for (count = 0; count < 8; count = count + 1) begin
1261        mem[count] = INIT_00[(count * 32) +: 32];
1262        mem[8 * 1 + count] = INIT_01[(count * 32) +: 32];
1263        mem[8 * 2 + count] = INIT_02[(count * 32) +: 32];
1264        mem[8 * 3 + count] = INIT_03[(count * 32) +: 32];
1265        mem[8 * 4 + count] = INIT_04[(count * 32) +: 32];
1266        mem[8 * 5 + count] = INIT_05[(count * 32) +: 32];
1267        mem[8 * 6 + count] = INIT_06[(count * 32) +: 32];
1268        mem[8 * 7 + count] = INIT_07[(count * 32) +: 32];
1269        mem[8 * 8 + count] = INIT_08[(count * 32) +: 32];
1270        mem[8 * 9 + count] = INIT_09[(count * 32) +: 32];
1271        mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32];
1272        mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32];
1273        mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32];
1274        mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32];
1275        mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32];
1276        mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32];
1277        mem[8 * 16 + count] = INIT_10[(count * 32) +: 32];
1278        mem[8 * 17 + count] = INIT_11[(count * 32) +: 32];
1279        mem[8 * 18 + count] = INIT_12[(count * 32) +: 32];
1280        mem[8 * 19 + count] = INIT_13[(count * 32) +: 32];
1281        mem[8 * 20 + count] = INIT_14[(count * 32) +: 32];
1282        mem[8 * 21 + count] = INIT_15[(count * 32) +: 32];
1283        mem[8 * 22 + count] = INIT_16[(count * 32) +: 32];
1284        mem[8 * 23 + count] = INIT_17[(count * 32) +: 32];
1285        mem[8 * 24 + count] = INIT_18[(count * 32) +: 32];
1286        mem[8 * 25 + count] = INIT_19[(count * 32) +: 32];
1287        mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32];
1288        mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32];
1289        mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32];
1290        mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32];
1291        mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32];
1292        mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32];
1293        mem[8 * 32 + count] = INIT_20[(count * 32) +: 32];
1294        mem[8 * 33 + count] = INIT_21[(count * 32) +: 32];
1295        mem[8 * 34 + count] = INIT_22[(count * 32) +: 32];
1296        mem[8 * 35 + count] = INIT_23[(count * 32) +: 32];
1297        mem[8 * 36 + count] = INIT_24[(count * 32) +: 32];
1298        mem[8 * 37 + count] = INIT_25[(count * 32) +: 32];
1299        mem[8 * 38 + count] = INIT_26[(count * 32) +: 32];
1300        mem[8 * 39 + count] = INIT_27[(count * 32) +: 32];
1301        mem[8 * 40 + count] = INIT_28[(count * 32) +: 32];
1302        mem[8 * 41 + count] = INIT_29[(count * 32) +: 32];
1303        mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32];
1304        mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32];
1305        mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32];
1306        mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32];
1307        mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32];
1308        mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32];
1309        mem[8 * 48 + count] = INIT_30[(count * 32) +: 32];
1310        mem[8 * 49 + count] = INIT_31[(count * 32) +: 32];
1311        mem[8 * 50 + count] = INIT_32[(count * 32) +: 32];
1312        mem[8 * 51 + count] = INIT_33[(count * 32) +: 32];
1313        mem[8 * 52 + count] = INIT_34[(count * 32) +: 32];
1314        mem[8 * 53 + count] = INIT_35[(count * 32) +: 32];
1315        mem[8 * 54 + count] = INIT_36[(count * 32) +: 32];
1316        mem[8 * 55 + count] = INIT_37[(count * 32) +: 32];
1317        mem[8 * 56 + count] = INIT_38[(count * 32) +: 32];
1318        mem[8 * 57 + count] = INIT_39[(count * 32) +: 32];
1319        mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32];
1320        mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32];
1321        mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32];
1322        mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32];
1323        mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32];
1324        mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32];
1325    end
1326
1327// initiate parity start
1328    for (countp = 0; countp < 64; countp = countp + 1) begin
1329        memp[countp] = INITP_00[(countp * 4) +: 4];
1330        memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4];
1331        memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4];
1332        memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4];
1333        memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4];
1334        memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4];
1335        memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4];
1336        memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4];
1337    end
1338// initiate parity end
1339    
1340    change_clka <= 0;
1341    change_clkb <= 0;
1342    data_collision <= 0;
1343    data_collision_a_b <= 0;
1344    data_collision_b_a <= 0;
1345    memory_collision <= 0;
1346    memory_collision_a_b <= 0;
1347    memory_collision_b_a <= 0;
1348    setup_all_a_b <= 0;
1349    setup_all_b_a <= 0;
1350    setup_zero <= 0;
1351    setup_rf_a_b <= 0;
1352    setup_rf_b_a <= 0;
1353    end
1354
1355    assign data_addra_int = addra_int * 2;
1356    assign data_addra_reg = addra_reg * 2;
1357    assign data_addrb_int = addrb_int * 32;
1358    assign data_addrb_reg = addrb_reg * 32;
1359
1360
1361    initial begin
1362
1363    display_flag = 1;
1364    output_flag = 1;
1365    
1366    case (SIM_COLLISION_CHECK)
1367
1368        "NONE" : begin
1369                 output_flag = 0;
1370                     display_flag = 0;
1371                 end
1372        "WARNING_ONLY" : output_flag = 0;
1373        "GENERATE_X_ONLY" : display_flag = 0;
1374        "ALL" : ;
1375
1376        default : begin
1377                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
1378                  $finish;
1379                  end
1380
1381    endcase // case(SIM_COLLISION_CHECK)
1382
1383    end // initial begin
1384
1385    
1386    always @(posedge clka_int) begin
1387    if ((output_flag || display_flag)) begin
1388        time_clka = $time;
1389        #0 time_clkb_clka = time_clka - time_clkb;
1390        change_clka = ~change_clka;
1391    end
1392    end
1393    
1394    always @(posedge clkb_int) begin
1395    if ((output_flag || display_flag)) begin
1396        time_clkb = $time;
1397        #0 time_clka_clkb = time_clkb - time_clka;
1398        change_clkb = ~change_clkb;
1399    end
1400    end
1401    
1402    always @(change_clkb) begin
1403    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
1404        setup_all_a_b = 1;
1405    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
1406        setup_rf_a_b = 1;
1407    end
1408
1409    always @(change_clka) begin
1410    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
1411        setup_all_b_a = 1;
1412    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
1413        setup_rf_b_a = 1;
1414    end
1415
1416    always @(change_clkb or change_clka) begin
1417    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
1418        setup_zero = 1;
1419    end
1420
1421    always @(posedge setup_zero) begin
1422    if ((ena_int == 1) && (wea_int == 1) &&
1423        (enb_int == 1) && (web_int == 1) &&
1424        (data_addra_int[14:5] == data_addrb_int[14:5]))
1425        memory_collision <= 1;
1426    end
1427
1428    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
1429    if ((ena_reg == 1) && (wea_reg == 1) &&
1430        (enb_int == 1) && (web_int == 1) &&
1431        (data_addra_reg[14:5] == data_addrb_int[14:5]))
1432        memory_collision_a_b <= 1;
1433    end
1434
1435    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
1436    if ((ena_int == 1) && (wea_int == 1) &&
1437        (enb_reg == 1) && (web_reg == 1) &&
1438        (data_addra_int[14:5] == data_addrb_reg[14:5]))
1439        memory_collision_b_a <= 1;
1440    end
1441
1442    always @(posedge setup_all_a_b) begin
1443    if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
1444    if ((ena_reg == 1) && (enb_int == 1)) begin
1445        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1446        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1447        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1448        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1449// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1450// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1451// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1452        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1453        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1454        6'b101011 : begin display_wa_wb; end
1455        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1456// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1457        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1458        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1459// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1460        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1461        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1462// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1463        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1464        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1465        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1466        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1467// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1468// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1469// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1470        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1471        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1472        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1473        endcase
1474    end
1475    end
1476    setup_all_a_b <= 0;
1477    end
1478
1479
1480    always @(posedge setup_all_b_a) begin
1481    if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
1482    if ((ena_int == 1) && (enb_reg == 1)) begin
1483        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1484        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1485// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1486        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1487        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1488// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1489        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1490        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1491        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1492        6'b101011 : begin display_wa_wb; end
1493        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1494        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1495        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1496        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1497        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1498        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1499        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1500        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1501        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1502        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1503        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1504        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1505// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1506// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1507// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1508        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1509        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1510        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1511        endcase
1512    end
1513    end
1514    setup_all_b_a <= 0;
1515    end
1516
1517
1518    always @(posedge setup_zero) begin
1519    if (data_addra_int[14:5] == data_addrb_int[14:5]) begin
1520    if ((ena_int == 1) && (enb_int == 1)) begin
1521        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
1522        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
1523        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
1524        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
1525        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
1526        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
1527        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
1528        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
1529        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
1530        6'b101011 : begin display_wa_wb; end
1531        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
1532// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
1533        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
1534        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
1535// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
1536        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
1537        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
1538// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
1539        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
1540        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
1541        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
1542        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
1543// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
1544// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
1545// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
1546        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
1547        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
1548        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
1549        endcase
1550    end
1551    end
1552    setup_zero <= 0;
1553    end
1554
1555    task display_ra_wb;
1556    begin
1557    if (display_flag)
1558        $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
1559    end
1560    endtask
1561
1562    task display_wa_rb;
1563    begin
1564    if (display_flag)
1565        $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
1566    end
1567    endtask
1568
1569    task display_wa_wb;
1570    begin
1571    if (display_flag)
1572        $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
1573    end
1574    endtask
1575
1576
1577    always @(posedge setup_rf_a_b) begin
1578    if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
1579    if ((ena_reg == 1) && (enb_int == 1)) begin
1580        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1581// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1582// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1583// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1584        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1585        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1586        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1587// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1588// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1589// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1590// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1591// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1592// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1593// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1594// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1595// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1596// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1597// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1598// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1599// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1600// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1601// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1602        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1603        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1604        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1605// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1606// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1607// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1608        endcase
1609    end
1610    end
1611    setup_rf_a_b <= 0;
1612    end
1613
1614
1615    always @(posedge setup_rf_b_a) begin
1616    if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
1617    if ((ena_int == 1) && (enb_reg == 1)) begin
1618        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1619// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1620        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1621// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1622// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1623        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1624// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1625// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1626        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1627// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1628// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1629        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1630// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1631// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1632        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1633// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1634// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1635        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1636// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1637// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1638// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1639// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1640// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1641// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1642// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1643// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1644// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1645// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1646        endcase
1647    end
1648    end
1649    setup_rf_b_a <= 0;
1650    end
1651
1652
1653    always @(posedge clka_int) begin
1654    if ((output_flag || display_flag)) begin
1655        addra_reg <= addra_int;
1656        ena_reg <= ena_int;
1657        ssra_reg <= ssra_int;
1658        wea_reg <= wea_int;
1659    end
1660    end
1661    
1662    always @(posedge clkb_int) begin
1663    if ((output_flag || display_flag)) begin
1664        addrb_reg <= addrb_int;
1665        enb_reg <= enb_int;
1666        ssrb_reg <= ssrb_int;
1667        web_reg <= web_int;
1668    end
1669    end
1670    
1671        
1672    // Data
1673    always @(posedge memory_collision) begin
1674    if ((output_flag || display_flag)) begin
1675        mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
1676        memory_collision <= 0;
1677    end
1678    
1679    end
1680
1681    always @(posedge memory_collision_a_b) begin
1682    if ((output_flag || display_flag)) begin
1683        mem[addra_reg[12:4]][addra_reg[3:0] * 2 +: 2] <= 2'bx;
1684        memory_collision_a_b <= 0;
1685    end
1686    end
1687    
1688    always @(posedge memory_collision_b_a) begin
1689    if ((output_flag || display_flag)) begin
1690        mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
1691        memory_collision_b_a <= 0;
1692    end
1693    end
1694    
1695    always @(posedge data_collision[1]) begin
1696    if (ssra_int == 0 && output_flag) begin
1697        doa_out <= #100 2'bX;
1698    end
1699    data_collision[1] <= 0;
1700    end
1701
1702    always @(posedge data_collision[0]) begin
1703    if (ssrb_int == 0 && output_flag) begin
1704        dob_out[addra_int[3:0] * 2 +: 2] <= #100 2'bX;
1705    end
1706    data_collision[0] <= 0;
1707    end
1708
1709    always @(posedge data_collision_a_b[1]) begin
1710    if (ssra_reg == 0 && output_flag) begin
1711        doa_out <= #100 2'bX;
1712    end
1713    data_collision_a_b[1] <= 0;
1714    end
1715
1716    always @(posedge data_collision_a_b[0]) begin
1717    if (ssrb_int == 0 && output_flag) begin
1718        dob_out[addra_reg[3:0] * 2 +: 2] <= #100 2'bX;
1719    end
1720    data_collision_a_b[0] <= 0;
1721    end
1722
1723    always @(posedge data_collision_b_a[1]) begin
1724    if (ssra_int == 0 && output_flag) begin
1725        doa_out <= #100 2'bX;
1726    end
1727    data_collision_b_a[1] <= 0;
1728    end
1729
1730    always @(posedge data_collision_b_a[0]) begin
1731    if (ssrb_reg == 0 && output_flag) begin
1732        dob_out[addra_int[3:0] * 2 +: 2] <= #100 2'bX;
1733    end
1734    data_collision_b_a[0] <= 0;
1735    end
1736
1737
1738    initial begin
1739    case (WRITE_MODE_A)
1740        "WRITE_FIRST" : wr_mode_a <= 2'b00;
1741        "READ_FIRST" : wr_mode_a <= 2'b01;
1742        "NO_CHANGE" : wr_mode_a <= 2'b10;
1743        default : begin
1744                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
1745                $finish;
1746                end
1747    endcase
1748    end
1749
1750    initial begin
1751    case (WRITE_MODE_B)
1752        "WRITE_FIRST" : wr_mode_b <= 2'b00;
1753        "READ_FIRST" : wr_mode_b <= 2'b01;
1754        "NO_CHANGE" : wr_mode_b <= 2'b10;
1755        default : begin
1756                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
1757                $finish;
1758                end
1759    endcase
1760    end
1761
1762
1763    // Port A
1764    always @(posedge clka_int) begin
1765
1766    if (ena_int == 1'b1) begin
1767
1768        if (ssra_int == 1'b1) begin
1769        {doa_out} <= #100 SRVAL_A;
1770        end
1771        else begin
1772        if (wea_int == 1'b1) begin
1773            if (wr_mode_a == 2'b00) begin
1774            doa_out <= #100 dia_int;
1775            end
1776            else if (wr_mode_a == 2'b01) begin
1777
1778            doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
1779
1780            end
1781        end
1782        else begin
1783
1784            doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
1785            
1786        end
1787        end
1788
1789        // memory
1790        if (wea_int == 1'b1) begin
1791        mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= dia_int;
1792        end
1793        
1794    end
1795    end
1796
1797
1798    // Port B
1799    always @(posedge clkb_int) begin
1800
1801    if (enb_int == 1'b1) begin
1802
1803        if (ssrb_int == 1'b1) begin
1804        {dopb_out, dob_out} <= #100 SRVAL_B;
1805        end
1806        else begin
1807        if (web_int == 1'b1) begin
1808            if (wr_mode_b == 2'b00) begin
1809            dob_out <= #100 dib_int;
1810            dopb_out <= #100 dipb_int;
1811            end
1812            else if (wr_mode_b == 2'b01) begin
1813            dob_out <= #100 mem[addrb_int];
1814            dopb_out <= #100 memp[addrb_int];
1815            end
1816        end
1817        else begin
1818            dob_out <= #100 mem[addrb_int];
1819            dopb_out <= #100 memp[addrb_int];
1820        end
1821        end
1822
1823        // memory
1824        if (web_int == 1'b1) begin
1825        mem[addrb_int] <= dib_int;
1826        memp[addrb_int] <= dipb_int;
1827        end
1828
1829    end
1830    end
1831
1832
1833endmodule
1834
1835`endif
1836

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