Root/Examples/sram_gpio/logic/sim/unisims/RAMB16_S2_S9.v

1// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S9.v,v 1.9.158.2 2007/03/09 18:13:18 patrickp Exp $
2///////////////////////////////////////////////////////////////////////////////
3// Copyright (c) 1995/2005 Xilinx, Inc.
4// All Right Reserved.
5///////////////////////////////////////////////////////////////////////////////
6// ____ ____
7// / /\/ /
8// /___/ \ / Vendor : Xilinx
9// \ \ \/ Version : 8.1i (I.13)
10// \ \ Description : Xilinx Functional Simulation Library Component
11// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
12// /___/ /\ Filename : RAMB16_S2_S9.v
13// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005
14// \___\/\___\
15//
16// Revision:
17// 03/23/04 - Initial version.
18// End Revision
19
20`ifdef legacy_model
21
22`timescale 1 ps / 1 ps
23
24module RAMB16_S2_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
25
26    parameter INIT_A = 2'h0;
27    parameter INIT_B = 9'h0;
28    parameter SRVAL_A = 2'h0;
29    parameter SRVAL_B = 9'h0;
30    parameter WRITE_MODE_A = "WRITE_FIRST";
31    parameter WRITE_MODE_B = "WRITE_FIRST";
32    parameter SIM_COLLISION_CHECK = "ALL";
33    localparam SETUP_ALL = 1000;
34    localparam SETUP_READ_FIRST = 3000;
35
36    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
37    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
38    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
39    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
40    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
41    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
42    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
43    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
44    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
45    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
46    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
47    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
48    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
49    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
50    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
51    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
52    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
53    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
54    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
55    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
56    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
57    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
58    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
59    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
60    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
61    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
62    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
63    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
64    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
65    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
66    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
67    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
68    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
69    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
70    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
71    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
72    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
73    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
74    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
75    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
76    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
77    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
78    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
79    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
80    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
81    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
82    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
83    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
84    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
85    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
86    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
87    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
88    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
89    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
90    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
91    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
92    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
93    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
94    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
95    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
96    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
97    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
98    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
99    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
100    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
101    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
102    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
103    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
104    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
105    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
106    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
107    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
108
109    output [1:0] DOA;
110    reg [1:0] doa_out;
111    wire doa_out0, doa_out1;
112
113    input [12:0] ADDRA;
114    input [1:0] DIA;
115    input ENA, CLKA, WEA, SSRA;
116
117    output [7:0] DOB;
118    output [0:0] DOPB;
119    reg [7:0] dob_out;
120    reg [0:0] dopb_out;
121    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7;
122    wire dopb0_out;
123
124    input [10:0] ADDRB;
125    input [7:0] DIB;
126    input [0:0] DIPB;
127    input ENB, CLKB, WEB, SSRB;
128
129    reg [18431:0] mem;
130    reg [8:0] count;
131    reg [1:0] wr_mode_a, wr_mode_b;
132
133    reg [5:0] dmi, dbi;
134    reg [5:0] pmi, pbi;
135
136    wire [12:0] addra_int;
137    reg [12:0] addra_reg;
138    wire [1:0] dia_int;
139    wire ena_int, clka_int, wea_int, ssra_int;
140    reg ena_reg, wea_reg, ssra_reg;
141    wire [10:0] addrb_int;
142    reg [10:0] addrb_reg;
143    wire [7:0] dib_int;
144    wire [0:0] dipb_int;
145    wire enb_int, clkb_int, web_int, ssrb_int;
146    reg display_flag;
147    reg enb_reg, web_reg, ssrb_reg;
148
149    time time_clka, time_clkb;
150    time time_clka_clkb;
151    time time_clkb_clka;
152
153    reg setup_all_a_b;
154    reg setup_all_b_a;
155    reg setup_zero;
156    reg setup_rf_a_b;
157    reg setup_rf_b_a;
158    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
159    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
160    reg address_collision, address_collision_a_b, address_collision_b_a;
161    reg change_clka;
162    reg change_clkb;
163
164    wire [14:0] data_addra_int;
165    wire [14:0] data_addra_reg;
166    wire [14:0] data_addrb_int;
167    wire [14:0] data_addrb_reg;
168    wire [15:0] parity_addra_int;
169    wire [15:0] parity_addra_reg;
170    wire [15:0] parity_addrb_int;
171    wire [15:0] parity_addrb_reg;
172
173    tri0 GSR = glbl.GSR;
174
175    always @(GSR)
176    if (GSR) begin
177        assign doa_out = INIT_A[1:0];
178        assign dob_out = INIT_B[7:0];
179        assign dopb_out = INIT_B[8:8];
180    end
181    else begin
182        deassign doa_out;
183        deassign dob_out;
184        deassign dopb_out;
185    end
186
187    buf b_doa_out0 (doa_out0, doa_out[0]);
188    buf b_doa_out1 (doa_out1, doa_out[1]);
189    buf b_dob_out0 (dob_out0, dob_out[0]);
190    buf b_dob_out1 (dob_out1, dob_out[1]);
191    buf b_dob_out2 (dob_out2, dob_out[2]);
192    buf b_dob_out3 (dob_out3, dob_out[3]);
193    buf b_dob_out4 (dob_out4, dob_out[4]);
194    buf b_dob_out5 (dob_out5, dob_out[5]);
195    buf b_dob_out6 (dob_out6, dob_out[6]);
196    buf b_dob_out7 (dob_out7, dob_out[7]);
197    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
198
199    buf b_doa0 (DOA[0], doa_out0);
200    buf b_doa1 (DOA[1], doa_out1);
201    buf b_dob0 (DOB[0], dob_out0);
202    buf b_dob1 (DOB[1], dob_out1);
203    buf b_dob2 (DOB[2], dob_out2);
204    buf b_dob3 (DOB[3], dob_out3);
205    buf b_dob4 (DOB[4], dob_out4);
206    buf b_dob5 (DOB[5], dob_out5);
207    buf b_dob6 (DOB[6], dob_out6);
208    buf b_dob7 (DOB[7], dob_out7);
209    buf b_dopb0 (DOPB[0], dopb_out0);
210
211    buf b_addra_0 (addra_int[0], ADDRA[0]);
212    buf b_addra_1 (addra_int[1], ADDRA[1]);
213    buf b_addra_2 (addra_int[2], ADDRA[2]);
214    buf b_addra_3 (addra_int[3], ADDRA[3]);
215    buf b_addra_4 (addra_int[4], ADDRA[4]);
216    buf b_addra_5 (addra_int[5], ADDRA[5]);
217    buf b_addra_6 (addra_int[6], ADDRA[6]);
218    buf b_addra_7 (addra_int[7], ADDRA[7]);
219    buf b_addra_8 (addra_int[8], ADDRA[8]);
220    buf b_addra_9 (addra_int[9], ADDRA[9]);
221    buf b_addra_10 (addra_int[10], ADDRA[10]);
222    buf b_addra_11 (addra_int[11], ADDRA[11]);
223    buf b_addra_12 (addra_int[12], ADDRA[12]);
224    buf b_dia_0 (dia_int[0], DIA[0]);
225    buf b_dia_1 (dia_int[1], DIA[1]);
226    buf b_ena (ena_int, ENA);
227    buf b_clka (clka_int, CLKA);
228    buf b_ssra (ssra_int, SSRA);
229    buf b_wea (wea_int, WEA);
230    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
231    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
232    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
233    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
234    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
235    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
236    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
237    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
238    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
239    buf b_addrb_9 (addrb_int[9], ADDRB[9]);
240    buf b_addrb_10 (addrb_int[10], ADDRB[10]);
241    buf b_dib_0 (dib_int[0], DIB[0]);
242    buf b_dib_1 (dib_int[1], DIB[1]);
243    buf b_dib_2 (dib_int[2], DIB[2]);
244    buf b_dib_3 (dib_int[3], DIB[3]);
245    buf b_dib_4 (dib_int[4], DIB[4]);
246    buf b_dib_5 (dib_int[5], DIB[5]);
247    buf b_dib_6 (dib_int[6], DIB[6]);
248    buf b_dib_7 (dib_int[7], DIB[7]);
249    buf b_dipb_0 (dipb_int[0], DIPB[0]);
250    buf b_enb (enb_int, ENB);
251    buf b_clkb (clkb_int, CLKB);
252    buf b_ssrb (ssrb_int, SSRB);
253    buf b_web (web_int, WEB);
254
255    initial begin
256    for (count = 0; count < 256; count = count + 1) begin
257        mem[count] <= INIT_00[count];
258        mem[256 * 1 + count] <= INIT_01[count];
259        mem[256 * 2 + count] <= INIT_02[count];
260        mem[256 * 3 + count] <= INIT_03[count];
261        mem[256 * 4 + count] <= INIT_04[count];
262        mem[256 * 5 + count] <= INIT_05[count];
263        mem[256 * 6 + count] <= INIT_06[count];
264        mem[256 * 7 + count] <= INIT_07[count];
265        mem[256 * 8 + count] <= INIT_08[count];
266        mem[256 * 9 + count] <= INIT_09[count];
267        mem[256 * 10 + count] <= INIT_0A[count];
268        mem[256 * 11 + count] <= INIT_0B[count];
269        mem[256 * 12 + count] <= INIT_0C[count];
270        mem[256 * 13 + count] <= INIT_0D[count];
271        mem[256 * 14 + count] <= INIT_0E[count];
272        mem[256 * 15 + count] <= INIT_0F[count];
273        mem[256 * 16 + count] <= INIT_10[count];
274        mem[256 * 17 + count] <= INIT_11[count];
275        mem[256 * 18 + count] <= INIT_12[count];
276        mem[256 * 19 + count] <= INIT_13[count];
277        mem[256 * 20 + count] <= INIT_14[count];
278        mem[256 * 21 + count] <= INIT_15[count];
279        mem[256 * 22 + count] <= INIT_16[count];
280        mem[256 * 23 + count] <= INIT_17[count];
281        mem[256 * 24 + count] <= INIT_18[count];
282        mem[256 * 25 + count] <= INIT_19[count];
283        mem[256 * 26 + count] <= INIT_1A[count];
284        mem[256 * 27 + count] <= INIT_1B[count];
285        mem[256 * 28 + count] <= INIT_1C[count];
286        mem[256 * 29 + count] <= INIT_1D[count];
287        mem[256 * 30 + count] <= INIT_1E[count];
288        mem[256 * 31 + count] <= INIT_1F[count];
289        mem[256 * 32 + count] <= INIT_20[count];
290        mem[256 * 33 + count] <= INIT_21[count];
291        mem[256 * 34 + count] <= INIT_22[count];
292        mem[256 * 35 + count] <= INIT_23[count];
293        mem[256 * 36 + count] <= INIT_24[count];
294        mem[256 * 37 + count] <= INIT_25[count];
295        mem[256 * 38 + count] <= INIT_26[count];
296        mem[256 * 39 + count] <= INIT_27[count];
297        mem[256 * 40 + count] <= INIT_28[count];
298        mem[256 * 41 + count] <= INIT_29[count];
299        mem[256 * 42 + count] <= INIT_2A[count];
300        mem[256 * 43 + count] <= INIT_2B[count];
301        mem[256 * 44 + count] <= INIT_2C[count];
302        mem[256 * 45 + count] <= INIT_2D[count];
303        mem[256 * 46 + count] <= INIT_2E[count];
304        mem[256 * 47 + count] <= INIT_2F[count];
305        mem[256 * 48 + count] <= INIT_30[count];
306        mem[256 * 49 + count] <= INIT_31[count];
307        mem[256 * 50 + count] <= INIT_32[count];
308        mem[256 * 51 + count] <= INIT_33[count];
309        mem[256 * 52 + count] <= INIT_34[count];
310        mem[256 * 53 + count] <= INIT_35[count];
311        mem[256 * 54 + count] <= INIT_36[count];
312        mem[256 * 55 + count] <= INIT_37[count];
313        mem[256 * 56 + count] <= INIT_38[count];
314        mem[256 * 57 + count] <= INIT_39[count];
315        mem[256 * 58 + count] <= INIT_3A[count];
316        mem[256 * 59 + count] <= INIT_3B[count];
317        mem[256 * 60 + count] <= INIT_3C[count];
318        mem[256 * 61 + count] <= INIT_3D[count];
319        mem[256 * 62 + count] <= INIT_3E[count];
320        mem[256 * 63 + count] <= INIT_3F[count];
321        mem[256 * 64 + count] <= INITP_00[count];
322        mem[256 * 65 + count] <= INITP_01[count];
323        mem[256 * 66 + count] <= INITP_02[count];
324        mem[256 * 67 + count] <= INITP_03[count];
325        mem[256 * 68 + count] <= INITP_04[count];
326        mem[256 * 69 + count] <= INITP_05[count];
327        mem[256 * 70 + count] <= INITP_06[count];
328        mem[256 * 71 + count] <= INITP_07[count];
329    end
330    address_collision <= 0;
331    address_collision_a_b <= 0;
332    address_collision_b_a <= 0;
333    change_clka <= 0;
334    change_clkb <= 0;
335    data_collision <= 0;
336    data_collision_a_b <= 0;
337    data_collision_b_a <= 0;
338    memory_collision <= 0;
339    memory_collision_a_b <= 0;
340    memory_collision_b_a <= 0;
341    setup_all_a_b <= 0;
342    setup_all_b_a <= 0;
343    setup_zero <= 0;
344    setup_rf_a_b <= 0;
345    setup_rf_b_a <= 0;
346    end
347
348    assign data_addra_int = addra_int * 2;
349    assign data_addra_reg = addra_reg * 2;
350    assign data_addrb_int = addrb_int * 8;
351    assign data_addrb_reg = addrb_reg * 8;
352    assign parity_addrb_int = 16384 + addrb_int * 1;
353    assign parity_addrb_reg = 16384 + addrb_reg * 1;
354
355
356    initial begin
357
358    display_flag = 1;
359
360    case (SIM_COLLISION_CHECK)
361
362        "NONE" : begin
363                 assign setup_all_a_b = 1'b0;
364                     assign setup_all_b_a = 1'b0;
365                     assign setup_zero = 1'b0;
366                     assign setup_rf_a_b = 1'b0;
367                     assign setup_rf_b_a = 1'b0;
368                     assign display_flag = 0;
369                 end
370        "WARNING_ONLY" : begin
371                         assign data_collision = 2'b00;
372                             assign data_collision_a_b = 2'b00;
373                             assign data_collision_b_a = 2'b00;
374                             assign memory_collision = 1'b0;
375                             assign memory_collision_a_b = 1'b0;
376                             assign memory_collision_b_a = 1'b0;
377                         end
378        "GENERATE_X_ONLY" : begin
379                            assign display_flag = 0;
380                            end
381        "ALL" : ;
382        default : begin
383                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
384                  $finish;
385                  end
386
387    endcase // case(SIM_COLLISION_CHECK)
388
389    end // initial begin
390
391
392    always @(posedge clka_int) begin
393    time_clka = $time;
394    #0 time_clkb_clka = time_clka - time_clkb;
395    change_clka = ~change_clka;
396    end
397
398    always @(posedge clkb_int) begin
399    time_clkb = $time;
400    #0 time_clka_clkb = time_clkb - time_clka;
401    change_clkb = ~change_clkb;
402    end
403
404    always @(change_clkb) begin
405    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
406        setup_all_a_b = 1;
407    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
408        setup_rf_a_b = 1;
409    end
410
411    always @(change_clka) begin
412    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
413        setup_all_b_a = 1;
414    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
415        setup_rf_b_a = 1;
416    end
417
418    always @(change_clkb or change_clka) begin
419    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
420        setup_zero = 1;
421    end
422
423    always @(posedge setup_zero) begin
424    if ((ena_int == 1) && (wea_int == 1) &&
425        (enb_int == 1) && (web_int == 1) &&
426        (data_addra_int[14:3] == data_addrb_int[14:3]))
427        memory_collision <= 1;
428    end
429
430    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
431    if ((ena_reg == 1) && (wea_reg == 1) &&
432        (enb_int == 1) && (web_int == 1) &&
433        (data_addra_reg[14:3] == data_addrb_int[14:3]))
434        memory_collision_a_b <= 1;
435    end
436
437    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
438    if ((ena_int == 1) && (wea_int == 1) &&
439        (enb_reg == 1) && (web_reg == 1) &&
440        (data_addra_int[14:3] == data_addrb_reg[14:3]))
441        memory_collision_b_a <= 1;
442    end
443
444    always @(posedge setup_all_a_b) begin
445    if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin
446    if ((ena_reg == 1) && (enb_int == 1)) begin
447        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
448        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
449        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
450        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
451// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
452// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
453// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
454        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
455        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
456        6'b101011 : begin display_wa_wb; end
457        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
458// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
459        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
460        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
461// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
462        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
463        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
464// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
465        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
466        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
467        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
468        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
469// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
470// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
471// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
472        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
473        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
474        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
475        endcase
476    end
477    end
478    setup_all_a_b <= 0;
479    end
480
481
482    always @(posedge setup_all_b_a) begin
483    if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin
484    if ((ena_int == 1) && (enb_reg == 1)) begin
485        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
486        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
487// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
488        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
489        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
490// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
491        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
492        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
493        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
494        6'b101011 : begin display_wa_wb; end
495        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
496        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
497        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
498        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
499        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
500        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
501        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
502        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
503        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
504        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
505        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
506        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
507// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
508// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
509// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
510        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
511        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
512        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
513        endcase
514    end
515    end
516    setup_all_b_a <= 0;
517    end
518
519
520    always @(posedge setup_zero) begin
521    if (data_addra_int[14:3] == data_addrb_int[14:3]) begin
522    if ((ena_int == 1) && (enb_int == 1)) begin
523        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
524        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
525        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
526        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
527        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
528        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
529        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
530        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
531        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
532        6'b101011 : begin display_wa_wb; end
533        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
534// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
535        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
536        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
537// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
538        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
539        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
540// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
541        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
542        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
543        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
544        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
545// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
546// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
547// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
548        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
549        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
550        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
551        endcase
552    end
553    end
554    setup_zero <= 0;
555    end
556
557    task display_ra_wb;
558    begin
559    if (display_flag)
560        $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
561    end
562    endtask
563
564    task display_wa_rb;
565    begin
566    if (display_flag)
567        $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
568    end
569    endtask
570
571    task display_wa_wb;
572    begin
573    if (display_flag)
574        $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
575    end
576    endtask
577
578
579    always @(posedge setup_rf_a_b) begin
580    if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin
581    if ((ena_reg == 1) && (enb_int == 1)) begin
582        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
583// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
584// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
585// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
586        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
587        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
588        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
589// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
590// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
591// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
592// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
593// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
594// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
595// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
596// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
597// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
598// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
599// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
600// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
601// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
602// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
603// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
604        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
605        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
606        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
607// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
608// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
609// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
610        endcase
611    end
612    end
613    setup_rf_a_b <= 0;
614    end
615
616
617    always @(posedge setup_rf_b_a) begin
618    if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin
619    if ((ena_int == 1) && (enb_reg == 1)) begin
620        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
621// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
622        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
623// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
624// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
625        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
626// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
627// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
628        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
629// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
630// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
631        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
632// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
633// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
634        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
635// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
636// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
637        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
638// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
639// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
640// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
641// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
642// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
643// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
644// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
645// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
646// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
647// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
648        endcase
649    end
650    end
651    setup_rf_b_a <= 0;
652    end
653
654
655    always @(posedge clka_int) begin
656    addra_reg <= addra_int;
657    ena_reg <= ena_int;
658    ssra_reg <= ssra_int;
659    wea_reg <= wea_int;
660    end
661
662    always @(posedge clkb_int) begin
663    addrb_reg <= addrb_int;
664    enb_reg <= enb_int;
665    ssrb_reg <= ssrb_int;
666    web_reg <= web_int;
667    end
668
669    // Data
670    always @(posedge memory_collision) begin
671    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
672        mem[data_addra_int + dmi] <= 1'bX;
673    end
674    memory_collision <= 0;
675    end
676
677    always @(posedge memory_collision_a_b) begin
678    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
679        mem[data_addra_reg + dmi] <= 1'bX;
680    end
681    memory_collision_a_b <= 0;
682    end
683
684    always @(posedge memory_collision_b_a) begin
685    for (dmi = 0; dmi < 2; dmi = dmi + 1) begin
686        mem[data_addra_int + dmi] <= 1'bX;
687    end
688    memory_collision_b_a <= 0;
689    end
690
691    always @(posedge data_collision[1]) begin
692    if (ssra_int == 0) begin
693        doa_out <= 2'bX;
694    end
695    data_collision[1] <= 0;
696    end
697
698    always @(posedge data_collision[0]) begin
699    if (ssrb_int == 0) begin
700        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
701        dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX;
702        end
703    end
704    data_collision[0] <= 0;
705    end
706
707    always @(posedge data_collision_a_b[1]) begin
708    if (ssra_reg == 0) begin
709        doa_out <= 2'bX;
710    end
711    data_collision_a_b[1] <= 0;
712    end
713
714    always @(posedge data_collision_a_b[0]) begin
715    if (ssrb_int == 0) begin
716        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
717        dob_out[data_addra_reg[2 : 0] + dbi] <= 1'bX;
718        end
719    end
720    data_collision_a_b[0] <= 0;
721    end
722
723    always @(posedge data_collision_b_a[1]) begin
724    if (ssra_int == 0) begin
725        doa_out <= 2'bX;
726    end
727    data_collision_b_a[1] <= 0;
728    end
729
730    always @(posedge data_collision_b_a[0]) begin
731    if (ssrb_reg == 0) begin
732        for (dbi = 0; dbi < 2; dbi = dbi + 1) begin
733        dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX;
734        end
735    end
736    data_collision_b_a[0] <= 0;
737    end
738
739
740    initial begin
741    case (WRITE_MODE_A)
742        "WRITE_FIRST" : wr_mode_a <= 2'b00;
743        "READ_FIRST" : wr_mode_a <= 2'b01;
744        "NO_CHANGE" : wr_mode_a <= 2'b10;
745        default : begin
746                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
747                $finish;
748                end
749    endcase
750    end
751
752    initial begin
753    case (WRITE_MODE_B)
754        "WRITE_FIRST" : wr_mode_b <= 2'b00;
755        "READ_FIRST" : wr_mode_b <= 2'b01;
756        "NO_CHANGE" : wr_mode_b <= 2'b10;
757        default : begin
758                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
759                $finish;
760                end
761    endcase
762    end
763
764    // Port A
765    always @(posedge clka_int) begin
766    if (ena_int == 1'b1) begin
767        if (ssra_int == 1'b1) begin
768        doa_out[0] <= SRVAL_A[0];
769        doa_out[1] <= SRVAL_A[1];
770        end
771        else begin
772        if (wea_int == 1'b1) begin
773            if (wr_mode_a == 2'b00) begin
774            doa_out <= dia_int;
775            end
776            else if (wr_mode_a == 2'b01) begin
777            doa_out[0] <= mem[data_addra_int + 0];
778            doa_out[1] <= mem[data_addra_int + 1];
779            end
780        end
781        else begin
782            doa_out[0] <= mem[data_addra_int + 0];
783            doa_out[1] <= mem[data_addra_int + 1];
784        end
785        end
786    end
787    end
788
789    always @(posedge clka_int) begin
790    if (ena_int == 1'b1 && wea_int == 1'b1) begin
791        mem[data_addra_int + 0] <= dia_int[0];
792        mem[data_addra_int + 1] <= dia_int[1];
793    end
794    end
795
796    // Port B
797    always @(posedge clkb_int) begin
798    if (enb_int == 1'b1) begin
799        if (ssrb_int == 1'b1) begin
800        dob_out[0] <= SRVAL_B[0];
801        dob_out[1] <= SRVAL_B[1];
802        dob_out[2] <= SRVAL_B[2];
803        dob_out[3] <= SRVAL_B[3];
804        dob_out[4] <= SRVAL_B[4];
805        dob_out[5] <= SRVAL_B[5];
806        dob_out[6] <= SRVAL_B[6];
807        dob_out[7] <= SRVAL_B[7];
808        dopb_out[0] <= SRVAL_B[8];
809        end
810        else begin
811        if (web_int == 1'b1) begin
812            if (wr_mode_b == 2'b00) begin
813            dob_out <= dib_int;
814            dopb_out <= dipb_int;
815            end
816            else if (wr_mode_b == 2'b01) begin
817            dob_out[0] <= mem[data_addrb_int + 0];
818            dob_out[1] <= mem[data_addrb_int + 1];
819            dob_out[2] <= mem[data_addrb_int + 2];
820            dob_out[3] <= mem[data_addrb_int + 3];
821            dob_out[4] <= mem[data_addrb_int + 4];
822            dob_out[5] <= mem[data_addrb_int + 5];
823            dob_out[6] <= mem[data_addrb_int + 6];
824            dob_out[7] <= mem[data_addrb_int + 7];
825            dopb_out[0] <= mem[parity_addrb_int + 0];
826            end
827        end
828        else begin
829            dob_out[0] <= mem[data_addrb_int + 0];
830            dob_out[1] <= mem[data_addrb_int + 1];
831            dob_out[2] <= mem[data_addrb_int + 2];
832            dob_out[3] <= mem[data_addrb_int + 3];
833            dob_out[4] <= mem[data_addrb_int + 4];
834            dob_out[5] <= mem[data_addrb_int + 5];
835            dob_out[6] <= mem[data_addrb_int + 6];
836            dob_out[7] <= mem[data_addrb_int + 7];
837            dopb_out[0] <= mem[parity_addrb_int + 0];
838        end
839        end
840    end
841    end
842
843    always @(posedge clkb_int) begin
844    if (enb_int == 1'b1 && web_int == 1'b1) begin
845        mem[data_addrb_int + 0] <= dib_int[0];
846        mem[data_addrb_int + 1] <= dib_int[1];
847        mem[data_addrb_int + 2] <= dib_int[2];
848        mem[data_addrb_int + 3] <= dib_int[3];
849        mem[data_addrb_int + 4] <= dib_int[4];
850        mem[data_addrb_int + 5] <= dib_int[5];
851        mem[data_addrb_int + 6] <= dib_int[6];
852        mem[data_addrb_int + 7] <= dib_int[7];
853        mem[parity_addrb_int + 0] <= dipb_int[0];
854    end
855    end
856
857    specify
858    (CLKA *> DOA) = (100, 100);
859    (CLKB *> DOB) = (100, 100);
860    (CLKB *> DOPB) = (100, 100);
861    endspecify
862
863endmodule
864
865`else
866
867// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S9.v,v 1.9.158.2 2007/03/09 18:13:18 patrickp Exp $
868///////////////////////////////////////////////////////////////////////////////
869// Copyright (c) 1995/2005 Xilinx, Inc.
870// All Right Reserved.
871///////////////////////////////////////////////////////////////////////////////
872// ____ ____
873// / /\/ /
874// /___/ \ / Vendor : Xilinx
875// \ \ \/ Version : 8.1i (I.13)
876// \ \ Description : Xilinx Timing Simulation Library Component
877// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
878// /___/ /\ Filename : RAMB16_S2_S9.v
879// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005
880// \___\/\___\
881//
882// Revision:
883// 03/23/04 - Initial version.
884// 03/10/05 - Initialized outputs.
885// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281).
886// End Revision
887
888`timescale 1 ps/1 ps
889
890module RAMB16_S2_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
891
892    parameter INIT_A = 2'h0;
893    parameter INIT_B = 9'h0;
894    parameter SRVAL_A = 2'h0;
895    parameter SRVAL_B = 9'h0;
896    parameter WRITE_MODE_A = "WRITE_FIRST";
897    parameter WRITE_MODE_B = "WRITE_FIRST";
898    parameter SIM_COLLISION_CHECK = "ALL";
899    localparam SETUP_ALL = 1000;
900    localparam SETUP_READ_FIRST = 3000;
901
902    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
903    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
904    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
905    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
906    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
907    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
908    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
909    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
910    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
911    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
912    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
913    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
914    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
915    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
916    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
917    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
918    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
919    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
920    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
921    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
922    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
923    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
924    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
925    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
926    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
927    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
928    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
929    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
930    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
931    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
932    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
933    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
934    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
935    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
936    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
937    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
938    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
939    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
940    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
941    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
942    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
943    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
944    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
945    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
946    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
947    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
948    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
949    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
950    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
951    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
952    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
953    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
954    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
955    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
956    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
957    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
958    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
959    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
960    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
961    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
962    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
963    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
964    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
965    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
966    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
967    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
968    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
969    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
970    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
971    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
972    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
973    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
974
975    output [1:0] DOA;
976    output [7:0] DOB;
977    output [0:0] DOPB;
978
979    input [12:0] ADDRA;
980    input [1:0] DIA;
981    input ENA, CLKA, WEA, SSRA;
982    input [10:0] ADDRB;
983    input [7:0] DIB;
984    input [0:0] DIPB;
985    input ENB, CLKB, WEB, SSRB;
986
987    reg [1:0] doa_out = INIT_A[1:0];
988    reg [7:0] dob_out = INIT_B[7:0];
989    reg [0:0] dopb_out = INIT_B[8:8];
990    
991    reg [7:0] mem [2047:0];
992    reg [0:0] memp [2047:0];
993    
994    reg [8:0] count, countp;
995    reg [1:0] wr_mode_a, wr_mode_b;
996
997    reg [5:0] dmi, dbi;
998    reg [5:0] pmi, pbi;
999
1000    wire [12:0] addra_int;
1001    reg [12:0] addra_reg;
1002    wire [1:0] dia_int;
1003    wire ena_int, clka_int, wea_int, ssra_int;
1004    reg ena_reg, wea_reg, ssra_reg;
1005    wire [10:0] addrb_int;
1006    reg [10:0] addrb_reg;
1007    wire [7:0] dib_int;
1008    wire [0:0] dipb_int;
1009    wire enb_int, clkb_int, web_int, ssrb_int;
1010    reg display_flag, output_flag;
1011    reg enb_reg, web_reg, ssrb_reg;
1012
1013    time time_clka, time_clkb;
1014    time time_clka_clkb;
1015    time time_clkb_clka;
1016
1017    reg setup_all_a_b;
1018    reg setup_all_b_a;
1019    reg setup_zero;
1020    reg setup_rf_a_b;
1021    reg setup_rf_b_a;
1022    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
1023    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
1024    reg change_clka;
1025    reg change_clkb;
1026
1027    wire [14:0] data_addra_int;
1028    wire [14:0] data_addra_reg;
1029    wire [14:0] data_addrb_int;
1030    wire [14:0] data_addrb_reg;
1031
1032    wire dia_enable = ena_int && wea_int;
1033    wire dib_enable = enb_int && web_int;
1034
1035    tri0 GSR = glbl.GSR;
1036    wire gsr_int;
1037
1038    buf b_gsr (gsr_int, GSR);
1039
1040    buf b_doa [1:0] (DOA, doa_out);
1041    buf b_addra [12:0] (addra_int, ADDRA);
1042    buf b_dia [1:0] (dia_int, DIA);
1043    buf b_ena (ena_int, ENA);
1044    buf b_clka (clka_int, CLKA);
1045    buf b_ssra (ssra_int, SSRA);
1046    buf b_wea (wea_int, WEA);
1047
1048    buf b_dob [7:0] (DOB, dob_out);
1049    buf b_dopb [0:0] (DOPB, dopb_out);
1050    buf b_addrb [10:0] (addrb_int, ADDRB);
1051    buf b_dib [7:0] (dib_int, DIB);
1052    buf b_dipb [0:0] (dipb_int, DIPB);
1053    buf b_enb (enb_int, ENB);
1054    buf b_clkb (clkb_int, CLKB);
1055    buf b_ssrb (ssrb_int, SSRB);
1056    buf b_web (web_int, WEB);
1057
1058    
1059    always @(gsr_int)
1060    if (gsr_int) begin
1061        assign {doa_out} = INIT_A;
1062        assign {dopb_out, dob_out} = INIT_B;
1063    end
1064    else begin
1065        deassign doa_out;
1066        deassign dob_out;
1067        deassign dopb_out;
1068    end
1069
1070    
1071    initial begin
1072
1073    for (count = 0; count < 32; count = count + 1) begin
1074        mem[count] = INIT_00[(count * 8) +: 8];
1075        mem[32 * 1 + count] = INIT_01[(count * 8) +: 8];
1076        mem[32 * 2 + count] = INIT_02[(count * 8) +: 8];
1077        mem[32 * 3 + count] = INIT_03[(count * 8) +: 8];
1078        mem[32 * 4 + count] = INIT_04[(count * 8) +: 8];
1079        mem[32 * 5 + count] = INIT_05[(count * 8) +: 8];
1080        mem[32 * 6 + count] = INIT_06[(count * 8) +: 8];
1081        mem[32 * 7 + count] = INIT_07[(count * 8) +: 8];
1082        mem[32 * 8 + count] = INIT_08[(count * 8) +: 8];
1083        mem[32 * 9 + count] = INIT_09[(count * 8) +: 8];
1084        mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8];
1085        mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8];
1086        mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8];
1087        mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8];
1088        mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8];
1089        mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8];
1090        mem[32 * 16 + count] = INIT_10[(count * 8) +: 8];
1091        mem[32 * 17 + count] = INIT_11[(count * 8) +: 8];
1092        mem[32 * 18 + count] = INIT_12[(count * 8) +: 8];
1093        mem[32 * 19 + count] = INIT_13[(count * 8) +: 8];
1094        mem[32 * 20 + count] = INIT_14[(count * 8) +: 8];
1095        mem[32 * 21 + count] = INIT_15[(count * 8) +: 8];
1096        mem[32 * 22 + count] = INIT_16[(count * 8) +: 8];
1097        mem[32 * 23 + count] = INIT_17[(count * 8) +: 8];
1098        mem[32 * 24 + count] = INIT_18[(count * 8) +: 8];
1099        mem[32 * 25 + count] = INIT_19[(count * 8) +: 8];
1100        mem[32 * 26 + count] = INIT_1A[(count * 8) +: 8];
1101        mem[32 * 27 + count] = INIT_1B[(count * 8) +: 8];
1102        mem[32 * 28 + count] = INIT_1C[(count * 8) +: 8];
1103        mem[32 * 29 + count] = INIT_1D[(count * 8) +: 8];
1104        mem[32 * 30 + count] = INIT_1E[(count * 8) +: 8];
1105        mem[32 * 31 + count] = INIT_1F[(count * 8) +: 8];
1106        mem[32 * 32 + count] = INIT_20[(count * 8) +: 8];
1107        mem[32 * 33 + count] = INIT_21[(count * 8) +: 8];
1108        mem[32 * 34 + count] = INIT_22[(count * 8) +: 8];
1109        mem[32 * 35 + count] = INIT_23[(count * 8) +: 8];
1110        mem[32 * 36 + count] = INIT_24[(count * 8) +: 8];
1111        mem[32 * 37 + count] = INIT_25[(count * 8) +: 8];
1112        mem[32 * 38 + count] = INIT_26[(count * 8) +: 8];
1113        mem[32 * 39 + count] = INIT_27[(count * 8) +: 8];
1114        mem[32 * 40 + count] = INIT_28[(count * 8) +: 8];
1115        mem[32 * 41 + count] = INIT_29[(count * 8) +: 8];
1116        mem[32 * 42 + count] = INIT_2A[(count * 8) +: 8];
1117        mem[32 * 43 + count] = INIT_2B[(count * 8) +: 8];
1118        mem[32 * 44 + count] = INIT_2C[(count * 8) +: 8];
1119        mem[32 * 45 + count] = INIT_2D[(count * 8) +: 8];
1120        mem[32 * 46 + count] = INIT_2E[(count * 8) +: 8];
1121        mem[32 * 47 + count] = INIT_2F[(count * 8) +: 8];
1122        mem[32 * 48 + count] = INIT_30[(count * 8) +: 8];
1123        mem[32 * 49 + count] = INIT_31[(count * 8) +: 8];
1124        mem[32 * 50 + count] = INIT_32[(count * 8) +: 8];
1125        mem[32 * 51 + count] = INIT_33[(count * 8) +: 8];
1126        mem[32 * 52 + count] = INIT_34[(count * 8) +: 8];
1127        mem[32 * 53 + count] = INIT_35[(count * 8) +: 8];
1128        mem[32 * 54 + count] = INIT_36[(count * 8) +: 8];
1129        mem[32 * 55 + count] = INIT_37[(count * 8) +: 8];
1130        mem[32 * 56 + count] = INIT_38[(count * 8) +: 8];
1131        mem[32 * 57 + count] = INIT_39[(count * 8) +: 8];
1132        mem[32 * 58 + count] = INIT_3A[(count * 8) +: 8];
1133        mem[32 * 59 + count] = INIT_3B[(count * 8) +: 8];
1134        mem[32 * 60 + count] = INIT_3C[(count * 8) +: 8];
1135        mem[32 * 61 + count] = INIT_3D[(count * 8) +: 8];
1136        mem[32 * 62 + count] = INIT_3E[(count * 8) +: 8];
1137        mem[32 * 63 + count] = INIT_3F[(count * 8) +: 8];
1138    end
1139
1140// initiate parity start
1141    for (countp = 0; countp < 256; countp = countp + 1) begin
1142        memp[countp] = INITP_00[(countp * 1) +: 1];
1143        memp[256 * 1 + countp] = INITP_01[(countp * 1) +: 1];
1144        memp[256 * 2 + countp] = INITP_02[(countp * 1) +: 1];
1145        memp[256 * 3 + countp] = INITP_03[(countp * 1) +: 1];
1146        memp[256 * 4 + countp] = INITP_04[(countp * 1) +: 1];
1147        memp[256 * 5 + countp] = INITP_05[(countp * 1) +: 1];
1148        memp[256 * 6 + countp] = INITP_06[(countp * 1) +: 1];
1149        memp[256 * 7 + countp] = INITP_07[(countp * 1) +: 1];
1150    end
1151// initiate parity end
1152    
1153    change_clka <= 0;
1154    change_clkb <= 0;
1155    data_collision <= 0;
1156    data_collision_a_b <= 0;
1157    data_collision_b_a <= 0;
1158    memory_collision <= 0;
1159    memory_collision_a_b <= 0;
1160    memory_collision_b_a <= 0;
1161    setup_all_a_b <= 0;
1162    setup_all_b_a <= 0;
1163    setup_zero <= 0;
1164    setup_rf_a_b <= 0;
1165    setup_rf_b_a <= 0;
1166    end
1167
1168    assign data_addra_int = addra_int * 2;
1169    assign data_addra_reg = addra_reg * 2;
1170    assign data_addrb_int = addrb_int * 8;
1171    assign data_addrb_reg = addrb_reg * 8;
1172
1173
1174    initial begin
1175
1176    display_flag = 1;
1177    output_flag = 1;
1178    
1179    case (SIM_COLLISION_CHECK)
1180
1181        "NONE" : begin
1182                 output_flag = 0;
1183                     display_flag = 0;
1184                 end
1185        "WARNING_ONLY" : output_flag = 0;
1186        "GENERATE_X_ONLY" : display_flag = 0;
1187        "ALL" : ;
1188
1189        default : begin
1190                  $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
1191                  $finish;
1192                  end
1193
1194    endcase // case(SIM_COLLISION_CHECK)
1195
1196    end // initial begin
1197
1198    
1199    always @(posedge clka_int) begin
1200    if ((output_flag || display_flag)) begin
1201        time_clka = $time;
1202        #0 time_clkb_clka = time_clka - time_clkb;
1203        change_clka = ~change_clka;
1204    end
1205    end
1206    
1207    always @(posedge clkb_int) begin
1208    if ((output_flag || display_flag)) begin
1209        time_clkb = $time;
1210        #0 time_clka_clkb = time_clkb - time_clka;
1211        change_clkb = ~change_clkb;
1212    end
1213    end
1214    
1215    always @(change_clkb) begin
1216    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
1217        setup_all_a_b = 1;
1218    if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
1219        setup_rf_a_b = 1;
1220    end
1221
1222    always @(change_clka) begin
1223    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
1224        setup_all_b_a = 1;
1225    if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
1226        setup_rf_b_a = 1;
1227    end
1228
1229    always @(change_clkb or change_clka) begin
1230    if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
1231        setup_zero = 1;
1232    end
1233
1234    always @(posedge setup_zero) begin
1235    if ((ena_int == 1) && (wea_int == 1) &&
1236        (enb_int == 1) && (web_int == 1) &&
1237        (data_addra_int[14:3] == data_addrb_int[14:3]))
1238        memory_collision <= 1;
1239    end
1240
1241    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
1242    if ((ena_reg == 1) && (wea_reg == 1) &&
1243        (enb_int == 1) && (web_int == 1) &&
1244        (data_addra_reg[14:3] == data_addrb_int[14:3]))
1245        memory_collision_a_b <= 1;
1246    end
1247
1248    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
1249    if ((ena_int == 1) && (wea_int == 1) &&
1250        (enb_reg == 1) && (web_reg == 1) &&
1251        (data_addra_int[14:3] == data_addrb_reg[14:3]))
1252        memory_collision_b_a <= 1;
1253    end
1254
1255    always @(posedge setup_all_a_b) begin
1256    if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin
1257    if ((ena_reg == 1) && (enb_int == 1)) begin
1258        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1259        6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1260        6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1261        6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1262// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1263// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1264// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1265        6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1266        6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
1267        6'b101011 : begin display_wa_wb; end
1268        6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1269// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1270        6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1271        6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1272// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1273        6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1274        6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1275// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1276        6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
1277        6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1278        6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1279        6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1280// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1281// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1282// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1283        6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1284        6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1285        6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1286        endcase
1287    end
1288    end
1289    setup_all_a_b <= 0;
1290    end
1291
1292
1293    always @(posedge setup_all_b_a) begin
1294    if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin
1295    if ((ena_int == 1) && (enb_reg == 1)) begin
1296        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1297        6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1298// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1299        6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1300        6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1301// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1302        6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
1303        6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1304        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1305        6'b101011 : begin display_wa_wb; end
1306        6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1307        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1308        6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1309        6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1310        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1311        6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1312        6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1313        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1314        6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1315        6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1316        6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1317        6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1318// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1319// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1320// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1321        6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1322        6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1323        6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
1324        endcase
1325    end
1326    end
1327    setup_all_b_a <= 0;
1328    end
1329
1330
1331    always @(posedge setup_zero) begin
1332    if (data_addra_int[14:3] == data_addrb_int[14:3]) begin
1333    if ((ena_int == 1) && (enb_int == 1)) begin
1334        case ({wr_mode_a, wr_mode_b, wea_int, web_int})
1335        6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
1336        6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
1337        6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
1338        6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
1339        6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
1340        6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
1341        6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
1342        6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
1343        6'b101011 : begin display_wa_wb; end
1344        6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
1345// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
1346        6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
1347        6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
1348// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
1349        6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
1350        6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
1351// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
1352        6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
1353        6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
1354        6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
1355        6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
1356// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
1357// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
1358// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
1359        6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
1360        6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
1361        6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
1362        endcase
1363    end
1364    end
1365    setup_zero <= 0;
1366    end
1367
1368    task display_ra_wb;
1369    begin
1370    if (display_flag)
1371        $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
1372    end
1373    endtask
1374
1375    task display_wa_rb;
1376    begin
1377    if (display_flag)
1378        $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
1379    end
1380    endtask
1381
1382    task display_wa_wb;
1383    begin
1384    if (display_flag)
1385        $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
1386    end
1387    endtask
1388
1389
1390    always @(posedge setup_rf_a_b) begin
1391    if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin
1392    if ((ena_reg == 1) && (enb_int == 1)) begin
1393        case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
1394// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1395// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1396// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1397        6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1398        6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
1399        6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
1400// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1401// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1402// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
1403// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1404// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1405// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1406// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1407// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1408// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1409// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1410// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1411// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
1412// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1413// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1414// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1415        6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1416        6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1417        6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
1418// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1419// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1420// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
1421        endcase
1422    end
1423    end
1424    setup_rf_a_b <= 0;
1425    end
1426
1427
1428    always @(posedge setup_rf_b_a) begin
1429    if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin
1430    if ((ena_int == 1) && (enb_reg == 1)) begin
1431        case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
1432// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1433        6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1434// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1435// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1436        6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
1437// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1438// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1439        6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
1440// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
1441// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1442        6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1443// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1444// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1445        6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1446// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1447// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1448        6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
1449// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
1450// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1451// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1452// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1453// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1454// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1455// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1456// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1457// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1458// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
1459        endcase
1460    end
1461    end
1462    setup_rf_b_a <= 0;
1463    end
1464
1465
1466    always @(posedge clka_int) begin
1467    if ((output_flag || display_flag)) begin
1468        addra_reg <= addra_int;
1469        ena_reg <= ena_int;
1470        ssra_reg <= ssra_int;
1471        wea_reg <= wea_int;
1472    end
1473    end
1474    
1475    always @(posedge clkb_int) begin
1476    if ((output_flag || display_flag)) begin
1477        addrb_reg <= addrb_int;
1478        enb_reg <= enb_int;
1479        ssrb_reg <= ssrb_int;
1480        web_reg <= web_int;
1481    end
1482    end
1483    
1484        
1485    // Data
1486    always @(posedge memory_collision) begin
1487    if ((output_flag || display_flag)) begin
1488        mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2] <= 2'bx;
1489        memory_collision <= 0;
1490    end
1491    
1492    end
1493
1494    always @(posedge memory_collision_a_b) begin
1495    if ((output_flag || display_flag)) begin
1496        mem[addra_reg[12:2]][addra_reg[1:0] * 2 +: 2] <= 2'bx;
1497        memory_collision_a_b <= 0;
1498    end
1499    end
1500    
1501    always @(posedge memory_collision_b_a) begin
1502    if ((output_flag || display_flag)) begin
1503        mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2] <= 2'bx;
1504        memory_collision_b_a <= 0;
1505    end
1506    end
1507    
1508    always @(posedge data_collision[1]) begin
1509    if (ssra_int == 0 && output_flag) begin
1510        doa_out <= #100 2'bX;
1511    end
1512    data_collision[1] <= 0;
1513    end
1514
1515    always @(posedge data_collision[0]) begin
1516    if (ssrb_int == 0 && output_flag) begin
1517        dob_out[addra_int[1:0] * 2 +: 2] <= #100 2'bX;
1518    end
1519    data_collision[0] <= 0;
1520    end
1521
1522    always @(posedge data_collision_a_b[1]) begin
1523    if (ssra_reg == 0 && output_flag) begin
1524        doa_out <= #100 2'bX;
1525    end
1526    data_collision_a_b[1] <= 0;
1527    end
1528
1529    always @(posedge data_collision_a_b[0]) begin
1530    if (ssrb_int == 0 && output_flag) begin
1531        dob_out[addra_reg[1:0] * 2 +: 2] <= #100 2'bX;
1532    end
1533    data_collision_a_b[0] <= 0;
1534    end
1535
1536    always @(posedge data_collision_b_a[1]) begin
1537    if (ssra_int == 0 && output_flag) begin
1538        doa_out <= #100 2'bX;
1539    end
1540    data_collision_b_a[1] <= 0;
1541    end
1542
1543    always @(posedge data_collision_b_a[0]) begin
1544    if (ssrb_reg == 0 && output_flag) begin
1545        dob_out[addra_int[1:0] * 2 +: 2] <= #100 2'bX;
1546    end
1547    data_collision_b_a[0] <= 0;
1548    end
1549
1550
1551    initial begin
1552    case (WRITE_MODE_A)
1553        "WRITE_FIRST" : wr_mode_a <= 2'b00;
1554        "READ_FIRST" : wr_mode_a <= 2'b01;
1555        "NO_CHANGE" : wr_mode_a <= 2'b10;
1556        default : begin
1557                $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
1558                $finish;
1559                end
1560    endcase
1561    end
1562
1563    initial begin
1564    case (WRITE_MODE_B)
1565        "WRITE_FIRST" : wr_mode_b <= 2'b00;
1566        "READ_FIRST" : wr_mode_b <= 2'b01;
1567        "NO_CHANGE" : wr_mode_b <= 2'b10;
1568        default : begin
1569                $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
1570                $finish;
1571                end
1572    endcase
1573    end
1574
1575
1576    // Port A
1577    always @(posedge clka_int) begin
1578
1579    if (ena_int == 1'b1) begin
1580
1581        if (ssra_int == 1'b1) begin
1582        {doa_out} <= #100 SRVAL_A;
1583        end
1584        else begin
1585        if (wea_int == 1'b1) begin
1586            if (wr_mode_a == 2'b00) begin
1587            doa_out <= #100 dia_int;
1588            end
1589            else if (wr_mode_a == 2'b01) begin
1590
1591            doa_out <= #100 mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2];
1592
1593            end
1594        end
1595        else begin
1596
1597            doa_out <= #100 mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2];
1598            
1599        end
1600        end
1601
1602        // memory
1603        if (wea_int == 1'b1) begin
1604        mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2] <= dia_int;
1605        end
1606        
1607    end
1608    end
1609
1610
1611    // Port B
1612    always @(posedge clkb_int) begin
1613
1614    if (enb_int == 1'b1) begin
1615
1616        if (ssrb_int == 1'b1) begin
1617        {dopb_out, dob_out} <= #100 SRVAL_B;
1618        end
1619        else begin
1620        if (web_int == 1'b1) begin
1621            if (wr_mode_b == 2'b00) begin
1622            dob_out <= #100 dib_int;
1623            dopb_out <= #100 dipb_int;
1624            end
1625            else if (wr_mode_b == 2'b01) begin
1626            dob_out <= #100 mem[addrb_int];
1627            dopb_out <= #100 memp[addrb_int];
1628            end
1629        end
1630        else begin
1631            dob_out <= #100 mem[addrb_int];
1632            dopb_out <= #100 memp[addrb_int];
1633        end
1634        end
1635
1636        // memory
1637        if (web_int == 1'b1) begin
1638        mem[addrb_int] <= dib_int;
1639        memp[addrb_int] <= dipb_int;
1640        end
1641
1642    end
1643    end
1644
1645
1646endmodule
1647
1648`endif
1649

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