Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	vlib work
2	vlog -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
3	vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
4	view wave
5	#do wave.do
6	add wave *
7	view structure
8	view signals
9	run 5us
10

Branches:
master