Root/Examples/sram_gpio/logic/sram_bus.v

1`timescale 1ns / 1ps
2module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led, irq_pin);
3  parameter B = (7);
4
5  input clk, nwe, ncs, noe, reset;
6  input [12:0] addr;
7  inout [B:0] sram_data;
8  output led;
9  input irq_pin;
10
11  // synchronize signals
12  reg sncs, snwe;
13  reg [12:0] buffer_addr;
14  reg [B:0] buffer_data;
15
16  // interfaz fpga signals
17// wire [12:0] addr;
18    
19  // bram interfaz signals
20  reg we;
21  reg w_st;
22
23  reg [B:0] wdBus;
24  wire [B:0] rdBus;
25
26  // interefaz signals assignments
27  wire T = ~noe | ncs;
28  assign sram_data = T?8'bZ:rdBus;
29  
30  //--------------------------------------------------------------------------
31
32  // synchronize assignment
33  always @(negedge clk)
34  begin
35    sncs <= ncs;
36    snwe <= nwe;
37    buffer_data <= sram_data;
38    buffer_addr <= addr;
39  end
40
41  // write access cpu to bram
42  always @(posedge clk)
43    if(~reset) {w_st, we, wdBus} <= 0;
44      else begin
45        wdBus <= buffer_data;
46        case (w_st)
47          0: begin
48              we <= 0;
49              if(sncs | snwe) w_st <= 1;
50          end
51          1: begin
52            if(~(sncs | snwe)) begin
53              we <= 1;
54              w_st <= 0;
55            end
56            else we <= 0;
57          end
58        endcase
59      end
60
61RAMB16_S2 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
62               .WE(we), .DI(wdBus[1:0]), .DO(rdBus[1:0]) );
63
64RAMB16_S2 ba1( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
65               .WE(we), .DI(wdBus[3:2]), .DO(rdBus[3:2]) );
66
67RAMB16_S2 ba2( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
68               .WE(we), .DI(wdBus[5:4]), .DO(rdBus[5:4]) );
69
70RAMB16_S2 ba3( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
71               .WE(we), .DI(wdBus[7:6]), .DO(rdBus[7:6]) );
72
73  reg [24:0] counter;
74  always @(posedge clk) begin
75    if (~reset)
76      counter <= {25{1'b0}};
77    else
78      counter <= counter + 1;
79  end
80  assign led = counter[24];
81
82endmodule
83
84

Archive Download this file

Branches:
master



interactive