Root/Examples/sram_gpio/logic/sram_bus_TB.v

1`timescale 1ns / 1ps
2
3module sram_bus_TB;
4
5   // inputs
6   reg clk;
7   reg [12:0] addr;
8   reg nwe;
9   reg ncs;
10   reg noe;
11   reg reset;
12   // leds
13   reg led;
14   // Bidirs
15   reg [7:0] sram_data$inout$reg ;
16
17   // Instantiate the Unit Under Test (UUT)
18   sram_bus uut ( .clk(clk), .reset(reset),
19       .sram_data(sram_data), .addr(addr), .nwe(nwe),
20       .ncs(ncs), .noe(noe)
21   );
22   parameter PERIOD = 20;
23   parameter real DUTY_CYCLE = 0.5;
24   parameter OFFSET = 0;
25   parameter TSET = 3;
26   parameter THLD = 3;
27   parameter NWS = 3;
28   parameter CAM_OFF = 4000;
29     
30     reg [15:0] i;
31     reg [15:0] j;
32     reg [15:0] k;
33     reg [15:0] data_tx;
34
35
36    event reset_trigger;
37    event reset_done_trigger;
38
39    initial begin // Reset the system, Start the image capture process
40      forever begin
41        @ (reset_trigger);
42        @ (negedge clk);
43        reset = 1;
44        @ (negedge clk);
45        reset = 0;
46        -> reset_done_trigger;
47      end
48    end
49     
50    initial begin // Initialize Inputs
51      clk = 0; addr = 0; nwe = 1; ncs = 1; noe = 1;
52    end
53
54   initial begin // Process for clk
55     #OFFSET;
56     forever
57     begin
58       clk = 1'b0;
59       #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
60       #(PERIOD*DUTY_CYCLE);
61     end
62   end
63
64 initial begin: TEST_CASE
65     #10 -> reset_trigger;
66     @ (reset_done_trigger);
67     // Write data to SRAM
68   for(i=0; i<10; i=i+1) begin
69     @ (posedge clk);
70     ncs <= 0;
71     addr <= i[9:0];
72     repeat (TSET) begin
73       @ (posedge clk);
74     end
75     nwe <= 0;
76     sram_data$inout$reg <= i*2;
77     repeat (NWS) begin
78       @ (posedge clk);
79     end
80     nwe <= 1;
81     repeat (THLD) begin
82       @ (posedge clk);
83     end
84     ncs <= 1;
85     sram_data$inout$reg = {16{1'bz}};
86   end
87   nwe = 1;
88
89   //Read Data
90   for(i=0; i<10; i=i+1) begin
91     @ (posedge clk);
92     ncs <= 0;
93     addr <= i[9:0];
94     repeat (TSET) begin
95       @ (posedge clk);
96     end
97     noe <= 0;
98     sram_data$inout$reg <= i;
99     repeat (NWS) begin
100       @ (posedge clk);
101     end
102     noe <= 1;
103     repeat (THLD) begin
104      @ (posedge clk);
105     end
106     ncs <= 1;
107     sram_data$inout$reg = {16{1'bz}};
108   end
109 end
110
111
112endmodule
113
114

Archive Download this file

Branches:
master



interactive