Hardware Design: SIE

Hardware Design: SIE Git Source Tree

Root/KICAD_design_files/SAKC_PCB/D_CONVERTER.sch

1	EESchema Schematic File Version 2 date Fri 23 Apr 2010 12:32:33 PM COT
2	LIBS:power,device,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,contrib,valves,./SAKC.cache
3	EELAYER 24 0
4	EELAYER END
5	$Descr A4 11700 8267
6	Sheet 5 9
7	Title ""
8	Date "23 feb 2010"
9	Rev ""
10	Comp ""
11	Comment1 ""
12	Comment2 ""
13	Comment3 ""
14	Comment4 ""
15	$EndDescr
16	Text HLabel 6600 2900 1 20 BiDi ~ 0
17	GND
18	Text HLabel 6000 2600 2 20 BiDi ~ 0
19	ANALOG[0..7]
20	Wire Bus Line
21	6000 2600 5950 2600
22	Wire Bus Line
23	5950 2600 5950 2200
24	Wire Wire Line
25	5850 2400 5400 2400
26	Wire Wire Line
27	5850 2300 5400 2300
28	Wire Wire Line
29	5850 2200 5400 2200
30	Wire Wire Line
31	5850 2100 5400 2100
32	Connection ~ 5600 2700
33	Wire Wire Line
34	5600 2700 5700 2700
35	Wire Wire Line
36	6600 2900 6600 2800
37	Wire Wire Line
38	6600 2800 6550 2800
39	Connection ~ 5600 2800
40	Connection ~ 4250 2100
41	Wire Wire Line
42	4250 2050 4250 2150
43	Wire Wire Line
44	4400 2300 4250 2300
45	Wire Wire Line
46	4400 2400 4250 2400
47	Wire Wire Line
48	4400 2600 4250 2600
49	Wire Wire Line
50	5600 2550 5600 2600
51	Wire Wire Line
52	5600 2600 5400 2600
53	Wire Wire Line
54	5400 2650 5600 2650
55	Wire Wire Line
56	5600 2650 5600 2950
57	Wire Wire Line
58	5600 2950 4900 2950
59	Wire Wire Line
60	4400 2650 4250 2650
61	Wire Wire Line
62	4400 2450 4250 2450
63	Wire Wire Line
64	4400 2350 4250 2350
65	Wire Wire Line
66	4250 2150 4400 2150
67	Wire Wire Line
68	4400 2100 4250 2100
69	Wire Wire Line
70	4900 1900 4900 1850
71	Wire Wire Line
72	5950 2800 5600 2800
73	Wire Wire Line
74	3750 2000 3750 1800
75	Wire Wire Line
76	5850 2150 5400 2150
77	Wire Wire Line
78	5850 2250 5400 2250
79	Wire Wire Line
80	5850 2350 5400 2350
81	Wire Wire Line
82	5850 2450 5400 2450
83	Entry Wire Line
84	5850 2450 5950 2550
85	Entry Wire Line
86	5850 2400 5950 2500
87	Entry Wire Line
88	5850 2350 5950 2450
89	Entry Wire Line
90	5850 2300 5950 2400
91	Entry Wire Line
92	5850 2250 5950 2350
93	Entry Wire Line
94	5850 2200 5950 2300
95	Entry Wire Line
96	5850 2150 5950 2250
97	Entry Wire Line
98	5850 2100 5950 2200
99	Text Label 5600 2450 2 20 ~ 0
100	ANALOG7
101	Text Label 5600 2400 2 20 ~ 0
102	ANALOG6
103	Text Label 5600 2350 2 20 ~ 0
104	ANALOG5
105	Text Label 5600 2300 2 20 ~ 0
106	ANALOG4
107	Text Label 5600 2250 2 20 ~ 0
108	ANALOG3
109	Text Label 5600 2200 2 20 ~ 0
110	ANALOG2
111	Text Label 5600 2150 2 20 ~ 0
112	ANALOG1
113	Text Label 5600 2100 2 20 ~ 0
114	ANALOG0
115	Text GLabel 5600 2550 2 20 BiDi ~ 0
116	3.3V
117	Text GLabel 4900 1850 3 20 BiDi ~ 0
118	3.3V
119	Text GLabel 4250 2050 3 20 BiDi ~ 0
120	3.3V
121	Text GLabel 3750 2000 1 20 BiDi ~ 0
122	3.3V
123	Text HLabel 3750 1800 3 20 BiDi ~ 0
124	3.3V
125	Text HLabel 5700 2700 2 20 BiDi ~ 0
126	AN_GND
127	Text HLabel 4250 2300 0 20 BiDi ~ 0
128	ADC_EOC
129	Text HLabel 4250 2350 0 20 BiDi ~ 0
130	ADC_CS
131	Text HLabel 4250 2400 0 20 BiDi ~ 0
132	ADC_CSTART
133	Text HLabel 4250 2450 0 20 BiDi ~ 0
134	ADC_SCLK
135	Text HLabel 4250 2600 0 20 BiDi ~ 0
136	ADC_SDIN
137	Text HLabel 4250 2650 0 20 BiDi ~ 0
138	ADC_SDOUT
139	$Comp
140	L INDUCTOR L12
141	U 1 1 4B7C62AC
142	P 6250 2800
143	F 0 "L12" V 6200 2800 40 0000 C CNN
144	F 1 "HZ0805C202R-00" V 6350 2800 40 0000 C CNN
145	1 6250 2800
146	0 -1 -1 0
147	$EndComp
148	$Comp
149	L TLV1548 U11
150	U 1 1 4B7C620D
151	P 4700 2900
152	F 0 "U11" H 4550 3800 60 0000 C CNN
153	F 1 "TLV1548" H 4700 2900 40 0000 C CNN
154	1 4700 2900
155	1 0 0 -1
156	$EndComp
157	$EndSCHEMATC
158

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Hardware Design: SIE

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Root/KICAD_design_files/SAKC_PCB/D_CONVERTER.sch

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