Hardware Design: SIE
Sign in or create your account | Project List | Help
Hardware Design: SIE Git Source Tree
Root/
| 1 | PCBNEW-LibModule-V1 23/2/2010-03:08:26 |
| 2 | $INDEX |
| 3 | J18 |
| 4 | $EndINDEX |
| 5 | $MODULE J18 |
| 6 | Po 0 0 0 15 43C58C74 4B8346A3 ~~ |
| 7 | Li J18 |
| 8 | Sc 4B8346A3 |
| 9 | AR |
| 10 | Op 0 0 0 |
| 11 | T0 0 -79 157 157 -2700 20 N V 21 "J18" |
| 12 | T1 0 118 118 118 -2700 20 N I 21 "HEADER 2" |
| 13 | DS -630 750 1620 750 80 26 |
| 14 | DS 1620 430 1620 -520 80 21 |
| 15 | DS 1620 -520 -630 -520 80 21 |
| 16 | DS -630 -520 -630 430 80 21 |
| 17 | DS -630 430 1620 430 80 21 |
| 18 | DS -630 1500 -630 1510 80 26 |
| 19 | DS -630 1510 -690 1570 80 26 |
| 20 | DS 1620 1500 -630 1500 80 26 |
| 21 | DS -630 1500 -630 -1500 80 26 |
| 22 | DS -630 -1500 1620 -1500 80 26 |
| 23 | DS 1620 -1500 1620 1500 80 26 |
| 24 | DS -730 1610 1660 1610 10 24 |
| 25 | DS 1660 1610 1660 -1540 10 24 |
| 26 | DS 1660 -1540 -730 -1540 10 24 |
| 27 | DS -730 -1540 -730 1610 10 24 |
| 28 | $PAD |
| 29 | Sh "1" R 620 620 0 0 0 |
| 30 | Dr 420 0 0 |
| 31 | At STD N 0CC08001 |
| 32 | Ne 68 "N17365986" |
| 33 | Po 0 0 |
| 34 | $EndPAD |
| 35 | $PAD |
| 36 | Sh "2" C 620 620 0 0 0 |
| 37 | Dr 420 0 0 |
| 38 | At STD N 0CC08001 |
| 39 | Ne 25 "BAT_V" |
| 40 | Po 1000 0 |
| 41 | $EndPAD |
| 42 | $EndMODULE J18 |
| 43 | $EndLIBRARY |
| 44 |
Branches:
master
