Hardware Design: SIE
Sign in or create your account | Project List | Help
Hardware Design: SIE Git Source Tree
Root/
| 1 | EESchema-LIBRARY Version 2.3 Date: 30/6/2009-14:23:47 |
| 2 | # |
| 3 | # SCIC |
| 4 | # |
| 5 | DEF SCIC U 0 40 Y Y 1 F N |
| 6 | F0 "U" -150 200 60 H V C C |
| 7 | F1 "SCIC" -50 -150 60 H V C C |
| 8 | DRAW |
| 9 | S -200 150 150 -100 0 1 0 N |
| 10 | X GND 4 200 -50 50 L 30 30 1 1 W |
| 11 | X NC 3 200 0 50 L 30 30 1 1 U |
| 12 | X STA 2 200 50 50 L 30 30 1 1 I |
| 13 | X A0 1 200 100 50 L 30 30 1 1 I |
| 14 | X SDA 5 -250 -50 50 R 30 30 1 1 B |
| 15 | X SCL 6 -250 0 50 R 30 30 1 1 I |
| 16 | X NC 7 -250 50 50 R 30 30 1 1 U |
| 17 | X VDD 8 -250 100 50 R 30 30 1 1 I |
| 18 | ENDDRAW |
| 19 | ENDDEF |
| 20 | # |
| 21 | #End Library |
| 22 |
Branches:
master
