Hardware Design: SIE
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| 1 | `timescale 1ns / 1ps |
| 2 | ////////////////////////////////////////////////////////////////////////////////// |
| 3 | // Company: UNAL |
| 4 | // Engineer: Ari Bejarano |
| 5 | // |
| 6 | // Create Date: 16:28:50 09/30/2010 |
| 7 | // Design Name: ps2_interface |
| 8 | // Module Name: ps2_interface |
| 9 | // Project Name: ps2_interface |
| 10 | // Target Devices: |
| 11 | // Tool versions: 2.0 |
| 12 | // Description: ¬¬ |
| 13 | // |
| 14 | // Dependencies: sync.v, writePulseGenerator.v, kb_ps2 |
| 15 | // |
| 16 | // Revision: |
| 17 | // Revision 0.01 - File Created |
| 18 | // Additional Comments: |
| 19 | // |
| 20 | ////////////////////////////////////////////////////////////////////////////////// |
| 21 | module ps2_interface(clk, data, addr, nwe, ncs, noe, reset, ps2_data, ps2_clk, irq_kb, led); |
| 22 | |
| 23 | parameter N = 13, M = 8;// M # de lineas de datos, N # de lineas de dirección |
| 24 | |
| 25 | input clk, nwe, ncs, noe, reset; |
| 26 | input [N-1:0] addr; |
| 27 | inout [M-1:0] data; |
| 28 | inout ps2_clk; |
| 29 | inout ps2_data; |
| 30 | output irq_kb; |
| 31 | output led; |
| 32 | |
| 33 | wire sncs; |
| 34 | wire snwe; |
| 35 | wire [N-1:0] buffer_addr; |
| 36 | wire [M-1:0] rdBus; |
| 37 | wire [M-1:0] wdBus; |
| 38 | wire we; |
| 39 | wire rx_done; |
| 40 | |
| 41 | assign led = ps2_clk; |
| 42 | |
| 43 | sync # (.N(13), .M(8))// M # de lineas de datos, N # de lineas de dirección |
| 44 | sync_U1(.clk(clk), |
| 45 | .data(data), |
| 46 | .addr(addr), |
| 47 | .nwe(nwe), |
| 48 | .ncs(ncs), |
| 49 | .noe(noe), |
| 50 | .rdBus(rdBus), |
| 51 | .sncs(sncs), |
| 52 | .snwe(snwe), |
| 53 | .buffer_addr(buffer_addr), |
| 54 | .buffer_data(wdBus)); |
| 55 | |
| 56 | writePulseGenerator writePulseGenerator_U2 (.clk(clk), |
| 57 | .snwe(snwe), |
| 58 | .sncs(sncs), |
| 59 | .reset(reset), |
| 60 | .we(we)); |
| 61 | |
| 62 | kb_ps2 kb_ps2_U3(.clk(~clk), |
| 63 | .reset(~reset), |
| 64 | .we_ps2(we), |
| 65 | .ps2_data(ps2_data), |
| 66 | .ps2_clk(ps2_clk), |
| 67 | .din(wdBus), |
| 68 | .rx_done(rx_done), |
| 69 | .tx_done(), |
| 70 | .dout(rdBus)); |
| 71 | |
| 72 | pulse_expander pulse_expander_U4( |
| 73 | .clk(clk), |
| 74 | .reset(~reset), |
| 75 | .pulse_in(rx_done), |
| 76 | .pulse_out(irq_kb) |
| 77 | ); |
| 78 | |
| 79 | |
| 80 | endmodule |
| 81 |
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