Root/PS2_INTERFACE/logic/ps2_interface_TF.v

1`timescale 1ns / 1ps
2
3////////////////////////////////////////////////////////////////////////////////
4// Company:
5// Engineer:
6//
7// Create Date: 10:48:20 10/15/2010
8// Design Name: ps2_interface
9// Module Name: /home/ari/Xilinx_Projects/ps2_interface/ps2_interface_TF.v
10// Project Name: ps2_interface
11// Target Device:
12// Tool versions:
13// Description:
14//
15// Verilog Test Fixture created by ISE for module: ps2_interface
16//
17// Dependencies:
18//
19// Revision:
20// Revision 0.01 - File Created
21// Additional Comments:
22//
23////////////////////////////////////////////////////////////////////////////////
24
25module ps2_interface_TF;
26
27    // Inputs
28    reg clk;
29    reg [12:0] addr;
30    reg nwe;
31    reg ncs;
32    reg noe;
33    reg reset;
34
35    // Outputs
36    wire irq_kb;
37  wire led;
38
39    // Bidirs
40    wire [7:0] data;
41    wire ps2_data;
42    wire ps2_clk;
43
44    reg ps2_datar;
45    reg ps2_clkr;
46  reg [7:0] datar;
47
48    // Instantiate the Unit Under Test (UUT)
49    ps2_interface uut (
50        .clk(clk),
51        .data(data),
52        .addr(addr),
53        .nwe(nwe),
54        .ncs(ncs),
55        .noe(noe),
56        .reset(reset),
57        .ps2_data(ps2_data),
58        .ps2_clk(ps2_clk),
59        .irq_kb(irq_kb),
60    .led(led)
61    );
62
63    initial begin
64        // Initialize Inputs
65        clk = 0;
66        addr = 0;
67        nwe = 1;
68        ncs = 0;
69        noe = 1;
70        reset = 1;
71    ps2_datar = 1;
72    ps2_clkr = 1;
73    datar = 8'bz;
74
75        // Wait 100 ns for global reset to finish
76        #100;
77        
78        // Add stimulus here
79    reset = 0;
80        #100;
81    reset = 1;
82    #100;
83    
84    //start
85    #25000;
86    ps2_datar=0;
87    #25000;
88    ps2_clkr=0;
89    #50000;
90    ps2_clkr=1;
91    
92    //data1
93    #25000;
94    ps2_datar=0;
95    #25000;
96    ps2_clkr=0;
97    #50000;
98    ps2_clkr=1;
99    
100    //data2
101    #25000;
102    ps2_datar=0;
103    #25000;
104    ps2_clkr=0;
105    #50000;
106    ps2_clkr=1;
107    
108    //data3
109    #25000;
110    ps2_datar=1;
111    #25000;
112    ps2_clkr=0;
113    #50000;
114    ps2_clkr=1;
115    
116    //data4
117    #25000;
118    ps2_datar=1;
119    #25000;
120    ps2_clkr=0;
121    #50000;
122    ps2_clkr=1;
123    
124    //data5
125    #25000;
126    ps2_datar=1;
127    #25000;
128    ps2_clkr=0;
129    #50000;
130    ps2_clkr=1;
131    
132    //data6
133    #25000;
134    ps2_datar=0;
135    #25000;
136    ps2_clkr=0;
137    #50000;
138    ps2_clkr=1;
139    
140    //data7
141    #25000;
142    ps2_datar=0;
143    #25000;
144    ps2_clkr=0;
145    #50000;
146    ps2_clkr=1;
147    
148    //data8
149    #25000;
150    ps2_datar=0;
151    #25000;
152    ps2_clkr=0;
153    #50000;
154    ps2_clkr=1;
155    
156    //parity
157    #25000;
158    ps2_datar=0;
159    #25000;
160    ps2_clkr=0;
161    #50000;
162    ps2_clkr=1;
163    
164    //stop
165    #25000;
166    ps2_datar=1;
167    #25000;
168    ps2_clkr=0;
169    #50000;
170    ps2_clkr=1;
171    
172    #50000;
173    datar=8'b01011010;
174    noe = 0;
175    nwe = 0;
176    ps2_datar=1'bz;
177    ps2_clkr=1'bz;
178    
179    #400
180    nwe = 1;
181    
182    #80000
183    ps2_clkr=0;
184    #50000
185    ps2_clkr=1;
186    #50000
187    ps2_clkr=0;
188    #50000
189    ps2_clkr=1;
190    #50000
191    ps2_clkr=0;
192    #50000
193    ps2_clkr=1;
194    #50000
195    ps2_clkr=0;
196    #50000
197    ps2_clkr=1;
198    #50000
199    ps2_clkr=0;
200    #50000
201    ps2_clkr=1;
202    #50000
203    ps2_clkr=0;
204    #50000
205    ps2_clkr=1;
206    #50000
207    ps2_clkr=0;
208    #50000
209    ps2_clkr=1;
210    #50000
211    ps2_clkr=0;
212    #50000
213    ps2_clkr=1;
214    #50000
215    ps2_clkr=0;
216    #50000
217    ps2_clkr=1;
218    #50000
219    ps2_clkr=0;
220    #50000
221    ps2_clkr=1;
222    #50000
223    ps2_clkr=0;
224    #50000
225    ps2_clkr=1;
226
227    end
228  
229  always
230    #10 clk=!clk;
231  
232  initial begin
233    $dumpfile ("ps2_interface_TF.vcd");
234    $dumpvars;
235  end
236  
237  initial begin
238    $display("\t\ttime,\tclk,\tdata,\taddr,\tnwe,\tncs,\tnoe,\treset,\tps2_data,\tps2_clk,\tirq_kb");
239    $monitor("%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d,\t%d",
240             $time,clk,data,addr,nwe,ncs,noe,reset,ps2_data,ps2_clk,irq_kb);
241  end
242  
243  initial
244   #3000000 $finish;
245   
246  assign ps2_clk=ps2_clkr;
247  assign ps2_data=ps2_datar;
248  assign data=datar;
249      
250endmodule
251
252

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