Hardware Design: SIE
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1 | `timescale 1ns / 1ps |
2 | |
3 | module ps2_rx( |
4 | input wire clk, reset, |
5 | input wire ps2_data, ps2_clk, rx_en, |
6 | output reg rx_done, |
7 | output wire [7:0] dout |
8 | ); |
9 | |
10 | //signal declaration |
11 | reg [1:0] state_reg, state_next; |
12 | reg [7:0] filter_reg; |
13 | wire [7:0] filter_next; |
14 | reg f_ps2c_reg; |
15 | wire f_ps2c_next; |
16 | reg [3:0] n_reg, n_next; |
17 | reg [10:0] b_reg, b_next; |
18 | wire fall_edge; |
19 | |
20 | //==================================================== |
21 | // falling - edge generation for ps2_clk |
22 | //==================================================== |
23 | always @(posedge clk, posedge reset) |
24 | if (reset) |
25 | begin |
26 | filter_reg <= 0; |
27 | f_ps2c_reg <= 0; |
28 | end |
29 | else |
30 | begin |
31 | filter_reg <= filter_next; |
32 | f_ps2c_reg <= f_ps2c_next; |
33 | end |
34 | |
35 | assign filter_next = {ps2_clk, filter_reg[7:1]}; |
36 | assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 : |
37 | (filter_reg==8'b00000000) ? 1'b0 : |
38 | f_ps2c_reg; |
39 | assign fall_edge = f_ps2c_reg & ~f_ps2c_next; |
40 | |
41 | //============================================================== |
42 | // FSM |
43 | //============================================================== |
44 | // state & data registers |
45 | always @(posedge clk, posedge reset) |
46 | if(reset) |
47 | begin |
48 | state_reg <= 1; |
49 | n_reg <= 0; |
50 | b_reg <= 0; |
51 | end |
52 | else |
53 | begin |
54 | state_reg <= state_next; |
55 | n_reg <= n_next; |
56 | b_reg <= b_next; |
57 | end |
58 | // next state logic |
59 | always @(*) |
60 | begin |
61 | state_next = state_reg; |
62 | n_next = n_reg; |
63 | b_next = b_reg; |
64 | rx_done = 1'b0; |
65 | case(state_reg) |
66 | 1: |
67 | if(fall_edge & rx_en) |
68 | begin |
69 | //shift in start bit |
70 | b_next = {ps2_data, b_reg[10:1]}; |
71 | n_next = 4'b1001; |
72 | state_next = 2; |
73 | end |
74 | 2: // 8 data + 1 parity + 1 stop |
75 | begin |
76 | if(fall_edge) |
77 | begin |
78 | b_next = {ps2_data, b_reg[10:1]}; |
79 | |
80 | if(n_reg==0) |
81 | state_next = 3; |
82 | else |
83 | n_next = n_reg-1; |
84 | end |
85 | end |
86 | 3: // 1 extra clock to complete the last shift |
87 | begin |
88 | state_next = 1; |
89 | rx_done = 1'b1; |
90 | end |
91 | default: state_next = 1; |
92 | endcase |
93 | end |
94 | |
95 | //output |
96 | assign dout = b_reg[8:1]; //data bits |
97 | |
98 | endmodule |
99 |
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