Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2	//////////////////////////////////////////////////////////////////////////////////
3	// Company: U.N
4	// Engineer: Ari Andrés Bejarano H.
5	//
6	// Create Date: 07:19:56 10/15/2010
7	// Design Name:
8	// Module Name: pulse_expander
9	// Project Name:
10	// Target Devices:
11	// Tool versions:
12	// Description: expande pulse_out = (pulse_in) + (num * pulses of clk)
13	//
14	// Dependencies:
15	//
16	// Revision:
17	// Revision 0.01 - File Created
18	// Additional Comments:
19	//
20	//////////////////////////////////////////////////////////////////////////////////
21	module pulse_expander(
22	input clk,
23	input reset,
24	input pulse_in,
25	output reg pulse_out
26	);
27
28	parameter num = 5000;
29
30	reg [24:0] cnt;
31	reg flag;
32
33	always@(posedge clk)begin
34
35	if(reset)
36	begin
37	cnt <= 0;
38	pulse_out <= 0;
39	flag <= 0;
40	end
41	else
42	if(pulse_in \|\| flag)
43	if(cnt < num)
44	begin
45	cnt <= cnt+1;
46	pulse_out <= 1;
47	flag <= 1;
48	end
49	else
50	begin
51	cnt <= 0;
52	pulse_out <= 0;
53	flag <= 0;
54	end
55	end
56
57	endmodule
58

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