Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2
3	////////////////////////////////////////////////////////////////////////////////
4	// Company:
5	// Engineer:
6	//
7	// Create Date: 08:01:22 10/15/2010
8	// Design Name: pulse_expander
9	// Module Name: /home/ari/Xilinx_Projects/keyboard/pulse_expander_TF.v
10	// Project Name: keyboard
11	// Target Device:
12	// Tool versions:
13	// Description:
14	//
15	// Verilog Test Fixture created by ISE for module: pulse_expander
16	//
17	// Dependencies:
18	//
19	// Revision:
20	// Revision 0.01 - File Created
21	// Additional Comments:
22	//
23	////////////////////////////////////////////////////////////////////////////////
24
25	module pulse_expander_TF;
26
27	// Inputs
28	reg clk;
29	reg reset;
30	reg pulse_in;
31
32	// Outputs
33	wire pulse_out;
34
35	// Instantiate the Unit Under Test (UUT)
36	pulse_expander uut (
37	.clk(clk),
38	.reset(reset),
39	.pulse_in(pulse_in),
40	.pulse_out(pulse_out)
41	);
42
43	initial begin
44	// Initialize Inputs
45	clk = 0;
46	reset = 0;
47	pulse_in = 0;
48
49	// Wait 100 ns for global reset to finish
50	#100;
51	// Add stimulus here
52	reset = 1;
53	#100;
54	reset = 0;
55	#100;
56	pulse_in = 1;
57	#20;
58	pulse_in = 0;
59	#400;
60	pulse_in = 1;
61	#20;
62	pulse_in = 0;
63	end
64
65	always
66	#10 clk=!clk;
67
68	initial begin
69	$dumpfile ("pulse_expander_TF.vcd");
70	$dumpvars;
71	end
72
73	initial begin
74	$display("\t\ttime,\tclk,\treset,\tpulse_in,\tpulse_out");
75	$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,pulse_in,pulse_out);
76	end
77
78	initial
79	#2000 $finish;
80
81	endmodule
82
83

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