Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2
3	module sync # (parameter N = 13, M = 8)
4	(input clk,
5	inout [M-1:0] data,
6	input [N-1:0] addr,
7	input nwe,
8	input ncs,
9	input noe,
10	input [M-1:0] rdBus,
11	output reg sncs,
12	output reg snwe,
13	output reg [N-1:0] buffer_addr,
14	output [M-1:0] buffer_data);
15
16
17	// interefaz signals assignments
18	wire T = ~noe \| ncs;
19	assign data = T?8'bZ:rdBus;
20	assign buffer_data = data;
21
22	// synchronize assignment
23	always @(negedge clk)
24	begin
25	sncs <= ncs;
26	snwe <= nwe;
27	buffer_addr <= addr;
28	end
29
30
31	endmodule
32

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