Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2
3	module writePulseGenerator (input clk,
4	input snwe,
5	input sncs,
6	input reset,
7	output reg we);
8
9	reg w_st;
10
11	// write access cpu to bram
12	always @(posedge clk)
13	if(~reset) {w_st, we} <= 0;
14	else begin
15
16	case (w_st)
17	0: begin
18	we <= 0;
19	if(sncs \| snwe)
20	w_st <= 1;
21	end
22	1: begin
23	if(~(sncs \| snwe))
24	begin
25	we <= 1;
26	w_st <= 0;
27	end
28	else we <= 0;
29	end
30	endcase
31	end
32
33	endmodule
34

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