Root/Software/sie_cg/templates/basic/jz_adc_peripheral.h

1/* ADC Peripheral.h
2
3Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
4                               Andres Calderon andres.calderon@emqbit.com
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
18Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
19
20#ifndef __adc_peripheral_h__
21#define __adc_peripheral_h__
22
23#define ADC_CMD_NONE 0x00 /* Nothing to do */
24#define ADC_CMD_SET_SPI_CLKDIV 0x00 /* Set clock divider for ADC sclk */
25#define ADC_CMD_SET_BUFFER_SIZE 0x00 /* Set clock divider for ADC sclk */
26
27#define ADC_CMD_SET_CHANNEL0 0x30 /* Set channel 0 */
28#define ADC_CMD_READ_CHANNEL0 0x20 /* Read channel 0 */
29
30#define ADC_CMD_SET_CHANNEL1 0x31 /* Set channel 1 */
31#define ADC_CMD_READ_CHANNEL1 0x21 /* Read channel 1 */
32
33#define ADC_CMD_SET_CHANNEL2 0x32 /* Set channel 2 */
34#define ADC_CMD_READ_CHANNEL2 0x22 /* Read channel 2 */
35
36#define ADC_CMD_SET_CHANNEL3 0x33 /* Set channel 3 */
37#define ADC_CMD_READ_CHANNEL3 0x23 /* Read channel 3 */
38
39#define ADC_CMD_SET_CHANNEL4 0x34 /* Set channel 4 */
40#define ADC_CMD_READ_CHANNEL4 0x24 /* Read channel 4 */
41
42#define ADC_CMD_SET_CHANNEL5 0x35 /* Set channel 5 */
43#define ADC_CMD_READ_CHANNEL5 0x25 /* Read channel 5 */
44
45#define ADC_CMD_SET_CHANNEL6 0x36 /* Set channel 6 */
46#define ADC_CMD_READ_CHANNEL6 0x26 /* Read channel 6 */
47
48#define ADC_CMD_SET_CHANNEL7 0x37 /* Set channel 7 */
49#define ADC_CMD_READ_CHANNEL7 0x27 /* Read channel 8 */
50
51#define ADC_CMD_SET_POWER_DOWN 0X38 /* Set ADC power down mode (1uA) */
52
53#define ADC_CMD_SET_FAST_CONV 0X39 /* Initialize ADC Fast Convertion(<10us)*/
54
55#define ADC_CMD_SET_LOW_CONV 0X3A /* Initialize ADC Slow Convertion(<40us)*/
56
57#define ADC_CMD_SET_AUTOSELFT_1 0x3B /* Set Autoselft ADC {(Vref+)-(Vref-)}/2*/
58#define ADC_CMD_READ_AUTOSELFT_1 0x2B /* Read Autoselft ADC 1 (0x0200) */
59
60#define ADC_CMD_SET_AUTOSELFT_2 0x3C /* Set Autoselft ADC (Vref-) */
61#define ADC_CMD_READ_AUTOSELFT_2 0x2C /* Read Autoselft ADC 2 (0x0000) */
62
63#define ADC_CMD_SET_AUTOSELFT_3 0x3D /* Set Autoselft ADC (Vref+) */
64#define ADC_CMD_READ_AUTOSELFT_3 0x2D /* Read Autoselft ADC 3 (0x03FF) */
65
66#define ADC_SPI_CLKDIV_MIN 0x08 /* 50/(2*9) -> 2.78MHz (MAX=2.8MHz) */
67#define ADC_SPI_CLKDIV_MAX 0xFF /* 50/(2*256) -> 97.65KHz */
68
69#define ADC_MAX_BUFFER 0x3FE/* 1022 reads/commands */
70
71
72typedef unsigned char uchar;
73typedef volatile unsigned int JZ_REG;
74
75static uchar ADC_SPI_CLKDIV=ADC_SPI_CLKDIV_MAX; //Set clock to minimum speed
76static int ADC_BUFFER_LEN=16;
77static int ADC_BUFFER_OFFSET= 8; //Ignore first 16 samples
78static uchar ADC_MUX_CHANNELS=0;
79
80void ADCTest(JZ_REG * ADCBuffer);
81void ADCPowerDown(JZ_REG * ADCBuffer);
82JZ_REG * ADCTakeSamples(JZ_REG * ADCBuffer,int CHANNEL);
83void ADCConfig(JZ_REG * ADCBuffer,uchar CMD);
84int ADCCheckBufferFull(JZ_REG * ADCBuffer);
85
86#endif
87

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