Hardware Design: SIE
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| 1 | /* |
| 2 | * SIE FPGA init |
| 3 | * |
| 4 | */ |
| 5 | |
| 6 | #include "jz_fpga_init.h" |
| 7 | |
| 8 | JZ_REG * |
| 9 | jz_cs2_init() |
| 10 | { |
| 11 | JZ_PIO *pio; |
| 12 | JZ_REG *virt_addr; |
| 13 | |
| 14 | pio = jz_gpio_map (CS2_PORT); |
| 15 | jz_gpio_as_func (pio, CS2_PIN, 0); |
| 16 | |
| 17 | virt_addr = (JZ_REG *) (jz_mmap(0x13010000) + 0x18); |
| 18 | |
| 19 | if (*virt_addr != 0x0FFF7700) |
| 20 | { |
| 21 | *virt_addr = 0x0FFF7700; |
| 22 | printf ("ADC: Configuring CS2 8 bits and 0 WS.\n"); |
| 23 | } |
| 24 | else |
| 25 | printf ("ADC: CS2, already configured.\n"); |
| 26 | |
| 27 | virt_addr = (JZ_REG *) jz_mmap (0x14000000); |
| 28 | return virt_addr; |
| 29 | } |
| 30 |
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