Root/UART/logic/build/project.log

1Release 10.1.03 - xst K.39 (lin)
2Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
3-->
4PMSPEC -- Overriding Xilinx file </opt/cad/Xilinx/10.1/ISE/spartan3/data/spartan3.acd> with local file </opt/cad/Xilinx/10.1/ISE/spartan3/data/spartan3.acd>
5
6TABLE OF CONTENTS
7  1) Synthesis Options Summary
8  2) HDL Compilation
9  3) Design Hierarchy Analysis
10  4) HDL Analysis
11  5) HDL Synthesis
12     5.1) HDL Synthesis Report
13  6) Advanced HDL Synthesis
14     6.1) Advanced HDL Synthesis Report
15  7) Low Level Synthesis
16  8) Partition Report
17  9) Final Report
18     9.1) Device utilization summary
19     9.2) Partition Resource Summary
20     9.3) TIMING REPORT
21
22
23=========================================================================
24* Synthesis Options Summary *
25=========================================================================
26---- Source Parameters
27Input File Name : "project.src"
28Input Format : mixed
29
30---- Target Parameters
31Target Device : xc3s500e-VQ100-4
32Output File Name : "project.ngc"
33Output Format : NGC
34
35---- Source Options
36Top Module Name : uart_peripheral
37
38---- General Options
39Optimization Goal : Area
40Optimization Effort : 1
41RTL Output : yes
42
43=========================================================================
44
45
46=========================================================================
47* HDL Compilation *
48=========================================================================
49Compiling verilog file "../uart_peripheral.v" in library work
50Compiling verilog file "../uart.v" in library work
51Module <uart_peripheral> compiled
52Module <UART> compiled
53Module <pc_buffrx_pc> compiled
54Module <pc_bufftx> compiled
55Module <pc_ctrl_rx> compiled
56Module <pc_ctrl_tx_pc> compiled
57Module <pc_dato_rdy> compiled
58Module <pc_div27> compiled
59Module <pc_div16> compiled
60Module <pc_div_ms> compiled
61Module <pc_ier> compiled
62Module <pc_if_arm_pc> compiled
63Module <pc_ifrxd> compiled
64Module <pc_isr> compiled
65Module <pc_lcr> compiled
66Module <pc_muestreo> compiled
67Module <pc_pulso> compiled
68No errors in compilation
69Analysis of file <"project.src"> succeeded.
70 
71
72=========================================================================
73* Design Hierarchy Analysis *
74=========================================================================
75Analyzing hierarchy for module <uart_peripheral> in library <work> with parameters.
76    B = "00000000000000000000000000000111"
77
78Analyzing hierarchy for module <UART> in library <work>.
79
80Analyzing hierarchy for module <pc_if_arm_pc> in library <work>.
81
82Analyzing hierarchy for module <pc_div27> in library <work>.
83
84Analyzing hierarchy for module <pc_div_ms> in library <work>.
85
86Analyzing hierarchy for module <pc_pulso> in library <work>.
87
88Analyzing hierarchy for module <pc_div16> in library <work>.
89
90Analyzing hierarchy for module <pc_ifrxd> in library <work>.
91
92Analyzing hierarchy for module <pc_muestreo> in library <work>.
93
94Analyzing hierarchy for module <pc_buffrx_pc> in library <work>.
95
96Analyzing hierarchy for module <pc_ctrl_rx> in library <work>.
97
98Analyzing hierarchy for module <pc_dato_rdy> in library <work>.
99
100Analyzing hierarchy for module <pc_bufftx> in library <work>.
101
102Analyzing hierarchy for module <pc_ctrl_tx_pc> in library <work>.
103
104Analyzing hierarchy for module <pc_ier> in library <work>.
105
106Analyzing hierarchy for module <pc_lcr> in library <work>.
107
108Analyzing hierarchy for module <pc_isr> in library <work>.
109
110
111=========================================================================
112* HDL Analysis *
113=========================================================================
114Analyzing top module <uart_peripheral>.
115    B = 32'sb00000000000000000000000000000111
116WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'CD' of instance 'UART' is tied to GND.
117WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'RI' of instance 'UART' is tied to GND.
118WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'DSR' of instance 'UART' is tied to GND.
119WARNING:Xst:852 - "../uart_peripheral.v" line 63: Unconnected input port 'CTS' of instance 'UART' is tied to GND.
120Module <uart_peripheral> is correct for synthesis.
121 
122Analyzing module <UART> in library <work>.
123Module <UART> is correct for synthesis.
124 
125Analyzing module <pc_if_arm_pc> in library <work>.
126Module <pc_if_arm_pc> is correct for synthesis.
127 
128Analyzing module <pc_div27> in library <work>.
129Module <pc_div27> is correct for synthesis.
130 
131Analyzing module <pc_div_ms> in library <work>.
132Module <pc_div_ms> is correct for synthesis.
133 
134Analyzing module <pc_pulso> in library <work>.
135Module <pc_pulso> is correct for synthesis.
136 
137Analyzing module <pc_div16> in library <work>.
138Module <pc_div16> is correct for synthesis.
139 
140Analyzing module <pc_ifrxd> in library <work>.
141Module <pc_ifrxd> is correct for synthesis.
142 
143Analyzing module <pc_muestreo> in library <work>.
144Module <pc_muestreo> is correct for synthesis.
145 
146Analyzing module <pc_buffrx_pc> in library <work>.
147Module <pc_buffrx_pc> is correct for synthesis.
148 
149Analyzing module <pc_ctrl_rx> in library <work>.
150Module <pc_ctrl_rx> is correct for synthesis.
151 
152Analyzing module <pc_dato_rdy> in library <work>.
153Module <pc_dato_rdy> is correct for synthesis.
154 
155Analyzing module <pc_bufftx> in library <work>.
156Module <pc_bufftx> is correct for synthesis.
157 
158Analyzing module <pc_ctrl_tx_pc> in library <work>.
159Module <pc_ctrl_tx_pc> is correct for synthesis.
160 
161Analyzing module <pc_ier> in library <work>.
162Module <pc_ier> is correct for synthesis.
163 
164Analyzing module <pc_lcr> in library <work>.
165Module <pc_lcr> is correct for synthesis.
166 
167Analyzing module <pc_isr> in library <work>.
168Module <pc_isr> is correct for synthesis.
169 
170
171=========================================================================
172* HDL Synthesis *
173=========================================================================
174
175Performing bidirectional port resolution...
176INFO:Xst:2679 - Register <buftx<10>> in unit <pc_bufftx> has a constant value of 1 during circuit operation. The register is replaced by logic.
177
178Synthesizing Unit <pc_if_arm_pc>.
179    Related source file is "../uart.v".
180WARNING:Xst:647 - Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
181WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
182WARNING:Xst:647 - Input <data_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
183WARNING:Xst:1780 - Signal <dato_tx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
184Unit <pc_if_arm_pc> synthesized.
185
186
187Synthesizing Unit <pc_div27>.
188    Related source file is "../uart.v".
189    Found 6-bit up counter for signal <div27>.
190    Summary:
191    inferred 1 Counter(s).
192Unit <pc_div27> synthesized.
193
194
195Synthesizing Unit <pc_div_ms>.
196    Related source file is "../uart.v".
197    Found 1-bit register for signal <clk_out>.
198    Found 16-bit register for signal <div>.
199    Found 16-bit adder for signal <div$addsub0000> created at line 581.
200    Found 16-bit comparator equal for signal <div$cmp_eq0000> created at line 574.
201    Found 16-bit register for signal <k_div>.
202    Summary:
203    inferred 33 D-type flip-flop(s).
204    inferred 1 Adder/Subtractor(s).
205    inferred 1 Comparator(s).
206Unit <pc_div_ms> synthesized.
207
208
209Synthesizing Unit <pc_pulso>.
210    Related source file is "../uart.v".
211    Found 1-bit register for signal <dff>.
212    Summary:
213    inferred 1 D-type flip-flop(s).
214Unit <pc_pulso> synthesized.
215
216
217Synthesizing Unit <pc_div16>.
218    Related source file is "../uart.v".
219    Found 4-bit up counter for signal <div16>.
220    Summary:
221    inferred 1 Counter(s).
222Unit <pc_div16> synthesized.
223
224
225Synthesizing Unit <pc_ifrxd>.
226    Related source file is "../uart.v".
227    Found 3-bit register for signal <ifrxd>.
228    Found 1-bit xor2 for signal <ifrxd_2$xor0000> created at line 967.
229    Found 1-bit xor2 for signal <ifrxd_2$xor0001> created at line 967.
230    Summary:
231    inferred 3 D-type flip-flop(s).
232Unit <pc_ifrxd> synthesized.
233
234
235Synthesizing Unit <pc_muestreo>.
236    Related source file is "../uart.v".
237    Found 1-bit register for signal <sample>.
238    Found 4-bit up counter for signal <cont_m>.
239    Found 1-bit register for signal <flag_rx>.
240    Summary:
241    inferred 1 Counter(s).
242    inferred 2 D-type flip-flop(s).
243Unit <pc_muestreo> synthesized.
244
245
246Synthesizing Unit <pc_buffrx_pc>.
247    Related source file is "../uart.v".
248    Found 1-bit register for signal <err_paridad>.
249    Found 8-bit register for signal <datorx>.
250    Found 1-bit register for signal <err_frame>.
251    Found 10-bit register for signal <bufrx>.
252    Found 1-bit xor9 for signal <iparity>.
253    Summary:
254    inferred 20 D-type flip-flop(s).
255    inferred 1 Xor(s).
256Unit <pc_buffrx_pc> synthesized.
257
258
259Synthesizing Unit <pc_ctrl_rx>.
260    Related source file is "../uart.v".
261    Found 1-bit register for signal <rx_lleno>.
262    Found 4-bit up counter for signal <cont_rx>.
263    Summary:
264    inferred 1 Counter(s).
265    inferred 1 D-type flip-flop(s).
266Unit <pc_ctrl_rx> synthesized.
267
268
269Synthesizing Unit <pc_dato_rdy>.
270    Related source file is "../uart.v".
271    Found 1-bit register for signal <dato_rdy>.
272    Found 1-bit register for signal <err_overrun>.
273    Summary:
274    inferred 2 D-type flip-flop(s).
275Unit <pc_dato_rdy> synthesized.
276
277
278Synthesizing Unit <pc_bufftx>.
279    Related source file is "../uart.v".
280    Found 10-bit register for signal <buftx<9:0>>.
281    Found 8-bit register for signal <dato_tx>.
282    Found 1-bit xor8 for signal <iparity>.
283    Summary:
284    inferred 18 D-type flip-flop(s).
285    inferred 1 Xor(s).
286Unit <pc_bufftx> synthesized.
287
288
289Synthesizing Unit <pc_ctrl_tx_pc>.
290    Related source file is "../uart.v".
291    Found 1-bit register for signal <tx_empty>.
292    Found 4-bit up counter for signal <cont_tx>.
293    Found 1-bit register for signal <tx_on>.
294    Summary:
295    inferred 1 Counter(s).
296    inferred 2 D-type flip-flop(s).
297Unit <pc_ctrl_tx_pc> synthesized.
298
299
300Synthesizing Unit <pc_ier>.
301    Related source file is "../uart.v".
302WARNING:Xst:647 - Input <data_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
303    Found 4-bit register for signal <IER>.
304    Summary:
305    inferred 4 D-type flip-flop(s).
306Unit <pc_ier> synthesized.
307
308
309Synthesizing Unit <pc_lcr>.
310    Related source file is "../uart.v".
311    Found 8-bit register for signal <LCR>.
312    Summary:
313    inferred 8 D-type flip-flop(s).
314Unit <pc_lcr> synthesized.
315
316
317Synthesizing Unit <pc_isr>.
318    Related source file is "../uart.v".
319WARNING:Xst:647 - Input <IER<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
320WARNING:Xst:646 - Signal <err_overrunm> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
321    Found 4-bit register for signal <ISR>.
322    Found 1-bit register for signal <aux1>.
323    Found 1-bit register for signal <carga_ISRd>.
324    Found 1-bit register for signal <mask_dato_rdy>.
325    Found 1-bit register for signal <mask_err_overrun>.
326    Found 1-bit register for signal <mask_error>.
327    Found 1-bit register for signal <mask_modem_int>.
328    Found 1-bit register for signal <mask_tx_empty>.
329    Summary:
330    inferred 11 D-type flip-flop(s).
331Unit <pc_isr> synthesized.
332
333
334Synthesizing Unit <UART>.
335    Related source file is "../uart.v".
336WARNING:Xst:647 - Input <CD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
337WARNING:Xst:1305 - Output <RTS> is never assigned. Tied to value 0.
338WARNING:Xst:647 - Input <CTS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
339WARNING:Xst:647 - Input <DSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
340WARNING:Xst:1305 - Output <DTR> is never assigned. Tied to value 0.
341WARNING:Xst:647 - Input <RI> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
342WARNING:Xst:653 - Signal <modem_int> is used but never assigned. This sourceless signal will be automatically connected to value 0.
343WARNING:Xst:653 - Signal <modem> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
344WARNING:Xst:1780 - Signal <error> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
345WARNING:Xst:1780 - Signal <dato_tx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
346WARNING:Xst:1780 - Signal <carga_div> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
347WARNING:Xst:646 - Signal <carga_MSR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
348WARNING:Xst:646 - Signal <carga_MCR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
349WARNING:Xst:646 - Signal <WordLength> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
350WARNING:Xst:646 - Signal <Stop> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
351WARNING:Xst:646 - Signal <Break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
352Unit <UART> synthesized.
353
354
355Synthesizing Unit <uart_peripheral>.
356    Related source file is "../uart_peripheral.v".
357WARNING:Xst:647 - Input <RxD2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
358WARNING:Xst:1306 - Output <TxD2> is never assigned.
359WARNING:Xst:646 - Signal <out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
360WARNING:Xst:646 - Signal <buffer_addr<12:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
361WARNING:Xst:1780 - Signal <RD> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
362WARNING:Xst:1780 - Signal <ISRC_LP> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
363    Found 8-bit tristate buffer for signal <sram_data>.
364    Found 13-bit register for signal <buffer_addr>.
365    Found 8-bit register for signal <buffer_data>.
366    Found 24-bit up counter for signal <counter>.
367    Found 1-bit register for signal <sncs>.
368    Found 1-bit register for signal <snwe>.
369    Found 1-bit register for signal <w_st>.
370    Found 8-bit register for signal <wdBus>.
371    Found 1-bit register for signal <we>.
372    Summary:
373    inferred 1 Counter(s).
374    inferred 33 D-type flip-flop(s).
375    inferred 8 Tristate(s).
376Unit <uart_peripheral> synthesized.
377
378
379=========================================================================
380HDL Synthesis Report
381
382Macro Statistics
383# Adders/Subtractors : 1
384 16-bit adder : 1
385# Counters : 6
386 24-bit up counter : 1
387 4-bit up counter : 4
388 6-bit up counter : 1
389# Registers : 71
390 1-bit register : 62
391 13-bit register : 1
392 16-bit register : 1
393 4-bit register : 2
394 8-bit register : 5
395# Comparators : 1
396 16-bit comparator equal : 1
397# Tristates : 1
398 8-bit tristate buffer : 1
399# Xors : 4
400 1-bit xor2 : 2
401 1-bit xor8 : 1
402 1-bit xor9 : 1
403
404=========================================================================
405
406=========================================================================
407* Advanced HDL Synthesis *
408=========================================================================
409
410Loading device for application Rf_Device from file '3s500e.nph' in environment /opt/cad/Xilinx/10.1/ISE:/opt/cad/Xilinx/10.1/ISE/.
411WARNING:Xst:1710 - FF/Latch <ISR_3> (without init value) has a constant value of 0 in block <pc_isr>. This FF/Latch will be trimmed during the optimization process.
412WARNING:Xst:2677 - Node <buffer_addr_3> of sequential type is unconnected in block <uart_peripheral>.
413WARNING:Xst:2677 - Node <buffer_addr_4> of sequential type is unconnected in block <uart_peripheral>.
414WARNING:Xst:2677 - Node <buffer_addr_5> of sequential type is unconnected in block <uart_peripheral>.
415WARNING:Xst:2677 - Node <buffer_addr_6> of sequential type is unconnected in block <uart_peripheral>.
416WARNING:Xst:2677 - Node <buffer_addr_7> of sequential type is unconnected in block <uart_peripheral>.
417WARNING:Xst:2677 - Node <buffer_addr_8> of sequential type is unconnected in block <uart_peripheral>.
418WARNING:Xst:2677 - Node <buffer_addr_9> of sequential type is unconnected in block <uart_peripheral>.
419WARNING:Xst:2677 - Node <buffer_addr_10> of sequential type is unconnected in block <uart_peripheral>.
420WARNING:Xst:2677 - Node <buffer_addr_11> of sequential type is unconnected in block <uart_peripheral>.
421WARNING:Xst:2677 - Node <buffer_addr_12> of sequential type is unconnected in block <uart_peripheral>.
422WARNING:Xst:2677 - Node <IER_3> of sequential type is unconnected in block <ier1>.
423WARNING:Xst:2677 - Node <mask_modem_int> of sequential type is unconnected in block <isr1>.
424
425=========================================================================
426Advanced HDL Synthesis Report
427
428Macro Statistics
429# Adders/Subtractors : 1
430 16-bit adder : 1
431# Counters : 6
432 24-bit up counter : 1
433 4-bit up counter : 4
434 6-bit up counter : 1
435# Registers : 128
436 Flip-Flops : 128
437# Comparators : 1
438 16-bit comparator equal : 1
439# Xors : 4
440 1-bit xor2 : 2
441 1-bit xor8 : 1
442 1-bit xor9 : 1
443
444=========================================================================
445
446=========================================================================
447* Low Level Synthesis *
448=========================================================================
449WARNING:Xst:2677 - Node <mask_modem_int> of sequential type is unconnected in block <pc_isr>.
450
451Optimizing unit <uart_peripheral> ...
452
453Optimizing unit <pc_div_ms> ...
454
455Optimizing unit <pc_buffrx_pc> ...
456
457Optimizing unit <pc_bufftx> ...
458
459Optimizing unit <pc_isr> ...
460WARNING:Xst:2677 - Node <UART/ier1/IER_3> of sequential type is unconnected in block <uart_peripheral>.
461
462Mapping all equations...
463Building and optimizing final netlist ...
464FlipFlop counter_23 has been replicated 1 time(s) to handle iob=true attribute.
465
466Final Macro Processing ...
467
468=========================================================================
469Final Register Report
470
471Macro Statistics
472# Registers : 173
473 Flip-Flops : 173
474
475=========================================================================
476
477=========================================================================
478* Partition Report *
479=========================================================================
480
481Partition Implementation Status
482-------------------------------
483
484  No Partitions were found in this design.
485
486-------------------------------
487
488=========================================================================
489* Final Report *
490=========================================================================
491Final Results
492RTL Top Level Output File Name : project.ngr
493Top Level Output File Name : project.ngc
494Output Format : NGC
495Optimization Goal : Area
496Keep Hierarchy : no
497
498Design Statistics
499# IOs : 22
500
501Cell Usage :
502# BELS : 278
503# GND : 1
504# INV : 9
505# LUT1 : 38
506# LUT2 : 10
507# LUT3 : 48
508# LUT4 : 78
509# MUXCY : 46
510# MUXF5 : 7
511# VCC : 1
512# XORCY : 40
513# FlipFlops/Latches : 173
514# FD : 3
515# FD_1 : 13
516# FDC : 10
517# FDCE : 80
518# FDE : 1
519# FDP : 1
520# FDPE : 14
521# FDR : 36
522# FDRE : 12
523# FDSE : 3
524# Clock Buffers : 1
525# BUFGP : 1
526# IO Buffers : 19
527# IBUF : 8
528# IOBUF : 8
529# OBUF : 3
530=========================================================================
531
532Device utilization summary:
533---------------------------
534
535Selected Device : 3s500evq100-4
536
537 Number of Slices: 114 out of 4656 2%
538 Number of Slice Flip Flops: 158 out of 9312 1%
539 Number of 4 input LUTs: 183 out of 9312 1%
540 Number of IOs: 22
541 Number of bonded IOBs: 20 out of 66 30%
542    IOB Flip Flops: 15
543 Number of GCLKs: 1 out of 24 4%
544
545---------------------------
546Partition Resource Summary:
547---------------------------
548
549  No Partitions were found in this design.
550
551---------------------------
552
553
554=========================================================================
555TIMING REPORT
556
557NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
558      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
559      GENERATED AFTER PLACE-and-ROUTE.
560
561Clock Information:
562------------------
563-----------------------------------+------------------------+-------+
564Clock Signal | Clock buffer(FF name) | Load |
565-----------------------------------+------------------------+-------+
566clk | BUFGP | 173 |
567-----------------------------------+------------------------+-------+
568
569Asynchronous Control Signals Information:
570----------------------------------------
571-----------------------------------+---------------------------+-------+
572Control Signal | Buffer(FF name) | Load |
573-----------------------------------+---------------------------+-------+
574reset_inv(reset_inv1_INV_0:O) | NONE(UART/bufftx1/buftx_9)| 105 |
575-----------------------------------+---------------------------+-------+
576
577Timing Summary:
578---------------
579Speed Grade: -4
580
581   Minimum period: 13.338ns (Maximum Frequency: 74.974MHz)
582   Minimum input arrival time before clock: 4.803ns
583   Maximum output required time after clock: 9.916ns
584   Maximum combinational path delay: 6.573ns
585
586Timing Detail:
587--------------
588All values displayed in nanoseconds (ns)
589
590=========================================================================
591Timing constraint: Default period analysis for Clock 'clk'
592  Clock period: 13.338ns (frequency: 74.974MHz)
593  Total number of paths / destination ports: 2891 / 269
594-------------------------------------------------------------------------
595Delay: 6.669ns (Levels of Logic = 3)
596  Source: buffer_addr_1 (FF)
597  Destination: UART/div_ms1/div_15 (FF)
598  Source Clock: clk falling
599  Destination Clock: clk rising
600
601  Data Path: buffer_addr_1 to UART/div_ms1/div_15
602                                Gate Net
603    Cell:in->out fanout Delay Delay Logical Name (Net Name)
604    ---------------------------------------- ------------
605     FD_1:C->Q 13 0.591 0.987 buffer_addr_1 (buffer_addr_1)
606     LUT4:I3->O 3 0.704 0.566 UART/if_arm1/data_out_cmp_eq00001 (UART/if_arm1/data_out_cmp_eq0000)
607     LUT3:I2->O 9 0.704 0.824 UART/if_arm1/carga_div_low1 (UART/carga_div_low)
608     LUT4:I3->O 16 0.704 1.034 UART/div_ms1/div_not00021 (UART/div_ms1/div_not0002)
609     FDCE:CE 0.555 UART/div_ms1/div_0
610    ----------------------------------------
611    Total 6.669ns (3.258ns logic, 3.411ns route)
612                                       (48.9% logic, 51.1% route)
613
614=========================================================================
615Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
616  Total number of paths / destination ports: 69 / 69
617-------------------------------------------------------------------------
618Offset: 4.803ns (Levels of Logic = 2)
619  Source: reset (PAD)
620  Destination: w_st (FF)
621  Destination Clock: clk rising
622
623  Data Path: reset to w_st
624                                Gate Net
625    Cell:in->out fanout Delay Delay Logical Name (Net Name)
626    ---------------------------------------- ------------
627     IBUF:I->O 6 1.218 0.669 reset_IBUF (reset_IBUF)
628     INV:I->O 155 0.704 1.301 reset_inv1_INV_0 (reset_inv)
629     FDR:R 0.911 w_st
630    ----------------------------------------
631    Total 4.803ns (2.833ns logic, 1.970ns route)
632                                       (59.0% logic, 41.0% route)
633
634=========================================================================
635Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
636  Total number of paths / destination ports: 169 / 11
637-------------------------------------------------------------------------
638Offset: 9.916ns (Levels of Logic = 5)
639  Source: buffer_addr_0 (FF)
640  Destination: sram_data<2> (PAD)
641  Source Clock: clk falling
642
643  Data Path: buffer_addr_0 to sram_data<2>
644                                Gate Net
645    Cell:in->out fanout Delay Delay Logical Name (Net Name)
646    ---------------------------------------- ------------
647     FD_1:C->Q 5 0.591 0.808 buffer_addr_0 (buffer_addr_0)
648     LUT2:I0->O 2 0.704 0.482 UART/if_arm1/data_out_or000111 (N6)
649     LUT4:I2->O 8 0.704 0.932 UART/if_arm1/data_out<0>11 (N01)
650     LUT4:I0->O 1 0.704 0.595 UART/if_arm1/data_out<2>4 (UART/if_arm1/data_out<2>4)
651     LUT4:I0->O 1 0.704 0.420 UART/if_arm1/data_out<2>14 (rdBus<2>)
652     IOBUF:I->IO 3.272 sram_data_2_IOBUF (sram_data<2>)
653    ----------------------------------------
654    Total 9.916ns (6.679ns logic, 3.237ns route)
655                                       (67.4% logic, 32.6% route)
656
657=========================================================================
658Timing constraint: Default path analysis
659  Total number of paths / destination ports: 16 / 8
660-------------------------------------------------------------------------
661Delay: 6.573ns (Levels of Logic = 3)
662  Source: ncs (PAD)
663  Destination: sram_data<7> (PAD)
664
665  Data Path: ncs to sram_data<7>
666                                Gate Net
667    Cell:in->out fanout Delay Delay Logical Name (Net Name)
668    ---------------------------------------- ------------
669     IBUF:I->O 2 1.218 0.622 ncs_IBUF (ncs_IBUF)
670     LUT2:I0->O 8 0.704 0.757 T1 (T)
671     IOBUF:T->IO 3.272 sram_data_7_IOBUF (sram_data<7>)
672    ----------------------------------------
673    Total 6.573ns (5.194ns logic, 1.379ns route)
674                                       (79.0% logic, 21.0% route)
675
676=========================================================================
677
678
679Total REAL time to Xst completion: 28.00 secs
680Total CPU time to Xst completion: 24.17 secs
681 
682-->
683
684
685Total memory usage is 143224 kilobytes
686
687Number of errors : 0 ( 0 filtered)
688Number of warnings : 49 ( 0 filtered)
689Number of infos : 1 ( 0 filtered)
690
691

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