Hardware Design: SIE
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| 1 | Release 10.1.03 Map K.39 (lin) |
| 2 | Xilinx Map Application Log File for Design 'uart_peripheral' |
| 3 | |
| 4 | Design Information |
| 5 | ------------------ |
| 6 | Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd |
| 7 | Target Device : xc3s500e |
| 8 | Target Package : vq100 |
| 9 | Target Speed : -4 |
| 10 | Mapper Version : spartan3e -- $Revision: 1.46.12.2 $ |
| 11 | Mapped Date : Thu Nov 11 14:37:58 2010 |
| 12 | |
| 13 | Mapping design into LUTs... |
| 14 | Writing file project.ngm... |
| 15 | Running directed packing... |
| 16 | Running delay-based LUT packing... |
| 17 | Running related packing... |
| 18 | Writing design file "project.ncd"... |
| 19 | |
| 20 | Design Summary |
| 21 | -------------- |
| 22 | |
| 23 | Design Summary: |
| 24 | Number of errors: 0 |
| 25 | Number of warnings: 2 |
| 26 | Logic Utilization: |
| 27 | Number of Slice Flip Flops: 157 out of 9,312 1% |
| 28 | Number of 4 input LUTs: 141 out of 9,312 1% |
| 29 | Logic Distribution: |
| 30 | Number of occupied Slices: 138 out of 4,656 2% |
| 31 | Number of Slices containing only related logic: 138 out of 138 100% |
| 32 | Number of Slices containing unrelated logic: 0 out of 138 0% |
| 33 | *See NOTES below for an explanation of the effects of unrelated logic. |
| 34 | Total Number of 4 input LUTs: 181 out of 9,312 1% |
| 35 | Number used as logic: 141 |
| 36 | Number used as a route-thru: 40 |
| 37 | Number of bonded IOBs: 20 out of 66 30% |
| 38 | IOB Flip Flops: 16 |
| 39 | Number of BUFGMUXs: 1 out of 24 4% |
| 40 | |
| 41 | Peak Memory Usage: 152 MB |
| 42 | Total REAL time to MAP completion: 10 secs |
| 43 | Total CPU time to MAP completion: 8 secs |
| 44 | |
| 45 | NOTES: |
| 46 | |
| 47 | Related logic is defined as being logic that shares connectivity - e.g. two |
| 48 | LUTs are "related" if they share common inputs. When assembling slices, |
| 49 | Map gives priority to combine logic that is related. Doing so results in |
| 50 | the best timing performance. |
| 51 | |
| 52 | Unrelated logic shares no connectivity. Map will only begin packing |
| 53 | unrelated logic into a slice once 99% of the slices are occupied through |
| 54 | related logic packing. |
| 55 | |
| 56 | Note that once logic distribution reaches the 99% level through related |
| 57 | logic packing, this does not mean the device is completely utilized. |
| 58 | Unrelated logic packing will then begin, continuing until all usable LUTs |
| 59 | and FFs are occupied. Depending on your timing budget, increased levels of |
| 60 | unrelated logic packing may adversely affect the overall timing performance |
| 61 | of your design. |
| 62 | |
| 63 | Mapping completed. |
| 64 | See MAP report file "project.mrp" for details. |
| 65 |
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