Root/UART/logic/build/project.mrp

1Release 10.1.03 Map K.39 (lin)
2Xilinx Mapping Report File for Design 'uart_peripheral'
3
4Design Information
5------------------
6Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
7Target Device : xc3s500e
8Target Package : vq100
9Target Speed : -4
10Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
11Mapped Date : Thu Nov 11 14:37:58 2010
12
13Design Summary
14--------------
15Number of errors: 0
16Number of warnings: 2
17Logic Utilization:
18  Number of Slice Flip Flops: 157 out of 9,312 1%
19  Number of 4 input LUTs: 141 out of 9,312 1%
20Logic Distribution:
21  Number of occupied Slices: 138 out of 4,656 2%
22    Number of Slices containing only related logic: 138 out of 138 100%
23    Number of Slices containing unrelated logic: 0 out of 138 0%
24      *See NOTES below for an explanation of the effects of unrelated logic.
25  Total Number of 4 input LUTs: 181 out of 9,312 1%
26    Number used as logic: 141
27    Number used as a route-thru: 40
28  Number of bonded IOBs: 20 out of 66 30%
29    IOB Flip Flops: 16
30  Number of BUFGMUXs: 1 out of 24 4%
31
32Peak Memory Usage: 152 MB
33Total REAL time to MAP completion: 10 secs
34Total CPU time to MAP completion: 8 secs
35
36NOTES:
37
38   Related logic is defined as being logic that shares connectivity - e.g. two
39   LUTs are "related" if they share common inputs. When assembling slices,
40   Map gives priority to combine logic that is related. Doing so results in
41   the best timing performance.
42
43   Unrelated logic shares no connectivity. Map will only begin packing
44   unrelated logic into a slice once 99% of the slices are occupied through
45   related logic packing.
46
47   Note that once logic distribution reaches the 99% level through related
48   logic packing, this does not mean the device is completely utilized.
49   Unrelated logic packing will then begin, continuing until all usable LUTs
50   and FFs are occupied. Depending on your timing budget, increased levels of
51   unrelated logic packing may adversely affect the overall timing performance
52   of your design.
53
54Table of Contents
55-----------------
56Section 1 - Errors
57Section 2 - Warnings
58Section 3 - Informational
59Section 4 - Removed Logic Summary
60Section 5 - Removed Logic
61Section 6 - IOB Properties
62Section 7 - RPMs
63Section 8 - Guide Report
64Section 9 - Area Group and Partition Summary
65Section 10 - Modular Design Summary
66Section 11 - Timing Report
67Section 12 - Configuration String Information
68Section 13 - Control Set Information
69Section 14 - Utilization by Hierarchy
70
71Section 1 - Errors
72------------------
73
74Section 2 - Warnings
75--------------------
76WARNING:LIT:243 - Logical network RxD2 has no load.
77WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
78   more times for the following (max. 5 shown):
79   TxD2
80   To see the details of these warning messages, please use the -detail switch.
81
82Section 3 - Informational
83-------------------------
84INFO:MapLib:564 - The following environment variables are currently set:
85INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1
86INFO:LIT:244 - All of the single ended outputs in this design are using slew
87   rate limited output drivers. The delay on speed critical single ended outputs
88   can be dramatically reduced by designating them as fast outputs.
89
90Section 4 - Removed Logic Summary
91---------------------------------
92   2 block(s) optimized away
93
94Section 5 - Removed Logic
95-------------------------
96
97Optimized Block(s):
98TYPE BLOCK
99GND XST_GND
100VCC XST_VCC
101
102To enable printing of redundant blocks removed and signals merged, set the
103detailed map report option and rerun map.
104
105Section 6 - IOB Properties
106--------------------------
107
108+-------------------------------------------------------------------------------------------------------------------------------------------------+
109| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
110| | | | | Strength | Rate | | | Delay |
111+-------------------------------------------------------------------------------------------------------------------------------------------------+
112| RxD | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
113| TxD | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
114| addr<0> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
115| addr<1> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
116| addr<2> | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
117| clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
118| irq_pin | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
119| led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | 0 / 0 |
120| ncs | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
121| noe | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
122| nwe | IBUF | INPUT | LVCMOS25 | | | IFF1 | | 0 / 3 |
123| reset | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
124| sram_data<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
125| sram_data<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
126| sram_data<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
127| sram_data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
128| sram_data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
129| sram_data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
130| sram_data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
131| sram_data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | IFF1 | | 0 / 3 |
132+-------------------------------------------------------------------------------------------------------------------------------------------------+
133
134Section 7 - RPMs
135----------------
136
137Section 8 - Guide Report
138------------------------
139Guide not run on this design.
140
141Section 9 - Area Group and Partition Summary
142--------------------------------------------
143
144Partition Implementation Status
145-------------------------------
146
147  No Partitions were found in this design.
148
149-------------------------------
150
151Area Group Information
152----------------------
153
154  No area groups were found in this design.
155
156----------------------
157
158Section 10 - Modular Design Summary
159-----------------------------------
160Modular Design not used for this design.
161
162Section 11 - Timing Report
163--------------------------
164This design was not run using timing mode.
165
166Section 12 - Configuration String Details
167-----------------------------------------
168Use the "-detail" map option to print out Configuration Strings
169
170Section 13 - Control Set Information
171------------------------------------
172No control set information for this architecture.
173
174Section 14 - Utilization by Hierarchy
175-------------------------------------
176+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
177| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name |
178+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
179| uart_peripheral/ | | 35/165 | 34/157 | 47/181 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | uart_peripheral |
180| +UART | | 0/130 | 0/123 | 0/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART |
181| ++buffrx1 | | 14/14 | 20/20 | 5/5 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/buffrx1 |
182| ++bufftx1 | | 12/12 | 17/17 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/bufftx1 |
183| ++ctrl_rx1 | | 3/3 | 5/5 | 6/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_rx1 |
184| ++ctrl_tx1 | | 6/6 | 6/6 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ctrl_tx1 |
185| ++dato_rdy1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/dato_rdy1 |
186| ++div161 | | 3/3 | 4/4 | 4/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div161 |
187| ++div27 | | 5/5 | 6/6 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div27 |
188| ++div_ms1 | | 31/31 | 33/33 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/div_ms1 |
189| ++ier1 | | 3/3 | 3/3 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ier1 |
190| ++if_arm1 | | 18/18 | 0/0 | 30/30 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/if_arm1 |
191| ++ifrxd1 | | 1/1 | 2/2 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/ifrxd1 |
192| ++isr1 | | 14/14 | 8/8 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/isr1 |
193| ++lcr1 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/lcr1 |
194| ++muestreo1 | | 7/7 | 6/6 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/muestreo1 |
195| ++pulso1 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso1 |
196| ++pulso2 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso2 |
197| ++pulso3 | | 2/2 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | uart_peripheral/UART/pulso3 |
198+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
199
200* Slices can be packed with basic elements from multiple hierarchies.
201  Therefore, a slice will be counted in every hierarchical module
202  that each of its packed basic elements belong to.
203** For each column, there are two numbers reported <A>/<B>.
204   <A> is the number of elements that belong to that specific hierarchical module.
205   <B> is the total number of elements from that hierarchical module and any lower level
206   hierarchical modules below.
207*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
208

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