Root/UART/logic/build/project_r.ll

1Revision 3
2; Created by bitgen K.39 at Thu Nov 11 14:39:12 2010
3; Bit lines have the following form:
4; <offset> <frame address> <frame offset> <information>
5; <information> may be zero or more <kw>=<value> pairs
6; Block=<blockname specifies the block associated with this
7; memory cell.
8;
9; Latch=<name> specifies the latch associated with this memory cell.
10;
11; Net=<netname> specifies the user net associated with this
12; memory cell.
13;
14; COMPARE=[YES | NO] specifies whether or not it is appropriate
15; to compare this bit position between a
16; "program" and a "readback" bitstream.
17; If not present the default is NO.
18;
19; Ram=<ram id>:<bit> This is used in cases where a CLB function
20; Rom=<ram id>:<bit> generator is used as RAM (or ROM). <Ram id>
21; will be either 'F', 'G', or 'M', indicating
22; that it is part of a single F or G function
23; generator used as RAM, or as a single RAM
24; (or ROM) built from both F and G. <Bit> is
25; a decimal number.
26;
27; Info lines have the following form:
28; Info <name>=<value> specifies a bit associated with the LCA
29; configuration options, and the value of
30; that bit. The names of these bits may have
31; special meaning to software reading the .ll file.
32;
33Info STARTSEL0=1
34Bit 9552 0x00000400 240 Block=P5 Latch=T2 Net=T
35Bit 9575 0x00000400 263 Block=P4 Latch=T2 Net=T
36Bit 10640 0x00000400 1328 Block=P10 Latch=T2 Net=T
37Bit 10663 0x00000400 1351 Block=P9 Latch=T2 Net=T
38Bit 10768 0x00000400 1456 Block=P12 Latch=T2 Net=T
39Bit 10791 0x00000400 1479 Block=P11 Latch=T2 Net=T
40Bit 10896 0x00000400 1584 Block=P16 Latch=T2 Net=T
41Bit 10919 0x00000400 1607 Block=P15 Latch=T2 Net=T
42Bit 12656 0x00020000 240 Block=P5 Latch=O2 Net=rdBus<6>
43Bit 12679 0x00020000 263 Block=P4 Latch=O2 Net=rdBus<7>
44Bit 13744 0x00020000 1328 Block=P10 Latch=O2 Net=rdBus<4>
45Bit 13767 0x00020000 1351 Block=P9 Latch=O2 Net=rdBus<5>
46Bit 13872 0x00020000 1456 Block=P12 Latch=O2 Net=rdBus<2>
47Bit 13895 0x00020000 1479 Block=P11 Latch=O2 Net=rdBus<3>
48Bit 14000 0x00020000 1584 Block=P16 Latch=O2 Net=rdBus<0>
49Bit 14023 0x00020000 1607 Block=P15 Latch=O2 Net=rdBus<1>
50Bit 15759 0x00020200 239 Block=P5 Latch=IQ1 Net=buffer_data<6>
51Bit 15784 0x00020200 264 Block=P4 Latch=IQ1 Net=buffer_data<7>
52Bit 16847 0x00020200 1327 Block=P10 Latch=IQ1 Net=buffer_data<4>
53Bit 16872 0x00020200 1352 Block=P9 Latch=IQ1 Net=buffer_data<5>
54Bit 16975 0x00020200 1455 Block=P12 Latch=IQ1 Net=buffer_data<2>
55Bit 17000 0x00020200 1480 Block=P11 Latch=IQ1 Net=buffer_data<3>
56Bit 17103 0x00020200 1583 Block=P16 Latch=IQ1 Net=buffer_data<0>
57Bit 17128 0x00020200 1608 Block=P15 Latch=IQ1 Net=buffer_data<1>
58Bit 131834 0x00062200 1466 Block=SLICE_X2Y48 Latch=YQ Net=wdBus<2>
59Bit 131837 0x00062200 1469 Block=SLICE_X2Y48 Latch=XQ Net=wdBus<3>
60Bit 131962 0x00062200 1594 Block=SLICE_X2Y44 Latch=YQ Net=wdBus<0>
61Bit 131965 0x00062200 1597 Block=SLICE_X2Y44 Latch=XQ Net=wdBus<1>
62Bit 901082 0x00202400 922 Block=SLICE_X26Y65 Latch=YQ Net=wdBus<4>
63Bit 901085 0x00202400 925 Block=SLICE_X26Y65 Latch=XQ Net=wdBus<5>
64Bit 903706 0x00220000 442 Block=SLICE_X27Y80 Latch=YQ Net=wdBus<6>
65Bit 903709 0x00220000 445 Block=SLICE_X27Y80 Latch=XQ Net=wdBus<7>
66Bit 909416 0x00220200 3048 Block=P30 Latch=I Net=reset_IBUF
67Bit 1019098 0x00242400 986 Block=SLICE_X30Y63 Latch=YQ Net=UART/buffrx1/datorx<6>
68Bit 1019101 0x00242400 989 Block=SLICE_X30Y63 Latch=XQ Net=UART/buffrx1/datorx<7>
69Bit 1019130 0x00242400 1018 Block=SLICE_X30Y62 Latch=YQ Net=UART/buffrx1/datorx<4>
70Bit 1019133 0x00242400 1021 Block=SLICE_X30Y62 Latch=XQ Net=UART/buffrx1/datorx<5>
71Bit 1080264 0x00280000 72 Block=P88 Latch=IQ1 Net=snwe
72Bit 1140058 0x002a0000 890 Block=SLICE_X34Y66 Latch=YQ Net=UART/buffrx1/datorx<0>
73Bit 1140061 0x002a0000 893 Block=SLICE_X34Y66 Latch=XQ Net=UART/buffrx1/datorx<1>
74Bit 1140090 0x002a0000 922 Block=SLICE_X34Y65 Latch=YQ Net=UART/buffrx1/bufrx<2>
75Bit 1140093 0x002a0000 925 Block=SLICE_X34Y65 Latch=XQ Net=UART/buffrx1/bufrx<3>
76Bit 1140186 0x002a0000 1018 Block=SLICE_X34Y62 Latch=YQ Net=UART/buffrx1/bufrx<4>
77Bit 1140189 0x002a0000 1021 Block=SLICE_X34Y62 Latch=XQ Net=UART/buffrx1/bufrx<5>
78Bit 1143162 0x002a0200 890 Block=SLICE_X35Y66 Latch=YQ Net=UART/buffrx1/bufrx<0>
79Bit 1143165 0x002a0200 893 Block=SLICE_X35Y66 Latch=XQ Net=UART/buffrx1/bufrx<1>
80Bit 1143226 0x002a0200 954 Block=SLICE_X35Y64 Latch=YQ Net=UART/buffrx1/datorx<2>
81Bit 1143229 0x002a0200 957 Block=SLICE_X35Y64 Latch=XQ Net=UART/buffrx1/datorx<3>
82Bit 1143258 0x002a0200 986 Block=SLICE_X35Y63 Latch=YQ Net=UART/buffrx1/bufrx<6>
83Bit 1143261 0x002a0200 989 Block=SLICE_X35Y63 Latch=XQ Net=UART/buffrx1/bufrx<7>
84Bit 1145416 0x002a0400 40 Block=P86 Latch=I Net=noe_IBUF
85Bit 1148463 0x002a0400 3087 Block=P38 Latch=I Net=clk_BUFGP/IBUFG
86Bit 1258042 0x002e0000 922 Block=SLICE_X38Y65 Latch=YQ Net=UART/buffrx1/err_frame
87Bit 1258077 0x002e0000 957 Block=SLICE_X38Y64 Latch=XQ Net=UART/buffrx1/err_paridad
88Bit 1260271 0x002e0200 47 Block=P84 Latch=IQ1 Net=buffer_addr<0>
89Bit 1260296 0x002e0200 72 Block=P83 Latch=IQ1 Net=buffer_addr<1>
90Bit 1261210 0x002e0200 986 Block=SLICE_X39Y63 Latch=YQ Net=UART/buffrx1/bufrx<8>
91Bit 1261213 0x002e0200 989 Block=SLICE_X39Y63 Latch=XQ Net=UART/buffrx1/bufrx<9>
92Bit 1317242 0x00300000 1146 Block=SLICE_X40Y58 Latch=YQ Net=UART/ctrl_rx1/cont_rx<2>
93Bit 1317245 0x00300000 1149 Block=SLICE_X40Y58 Latch=XQ Net=UART/ctrl_rx1/cont_rx<3>
94Bit 1319152 0x00300000 3056 Block=P44 Latch=O2 Net=Result<23>
95Bit 1320186 0x00300200 986 Block=SLICE_X41Y63 Latch=YQ Net=UART/pulso2/dff
96Bit 1320314 0x00300200 1114 Block=SLICE_X41Y59 Latch=YQ Net=UART/ctrl_rx1/cont_rx<0>
97Bit 1320317 0x00300200 1117 Block=SLICE_X41Y59 Latch=XQ Net=UART/ctrl_rx1/cont_rx<1>
98Bit 1376061 0x00320000 989 Block=SLICE_X42Y63 Latch=XQ Net=UART/muestreo1/sample
99Bit 1376093 0x00320000 1021 Block=SLICE_X42Y62 Latch=XQ Net=UART/muestreo1/cont_m<3>
100Bit 1379066 0x00320200 890 Block=SLICE_X43Y66 Latch=YQ Net=UART/isr1/mask_error
101Bit 1379162 0x00320200 986 Block=SLICE_X43Y63 Latch=YQ Net=UART/muestreo1/cont_m<2>
102Bit 1379194 0x00320200 1018 Block=SLICE_X43Y62 Latch=YQ Net=UART/muestreo1/cont_m<0>
103Bit 1379197 0x00320200 1021 Block=SLICE_X43Y62 Latch=XQ Net=UART/muestreo1/cont_m<1>
104Bit 1379293 0x00320200 1117 Block=SLICE_X43Y59 Latch=XQ Net=UART/ctrl_rx1/rx_lleno
105Bit 1380826 0x00320200 2650 Block=SLICE_X43Y11 Latch=YQ Net=counter<23>
106Bit 1380829 0x00320200 2653 Block=SLICE_X43Y11 Latch=XQ Net=counter<22>
107Bit 1380858 0x00320200 2682 Block=SLICE_X43Y10 Latch=YQ Net=counter<21>
108Bit 1380861 0x00320200 2685 Block=SLICE_X43Y10 Latch=XQ Net=counter<20>
109Bit 1380890 0x00320200 2714 Block=SLICE_X43Y9 Latch=YQ Net=counter<19>
110Bit 1380893 0x00320200 2717 Block=SLICE_X43Y9 Latch=XQ Net=counter<18>
111Bit 1380922 0x00320200 2746 Block=SLICE_X43Y8 Latch=YQ Net=counter<17>
112Bit 1380925 0x00320200 2749 Block=SLICE_X43Y8 Latch=XQ Net=counter<16>
113Bit 1380954 0x00320200 2778 Block=SLICE_X43Y7 Latch=YQ Net=counter<15>
114Bit 1380957 0x00320200 2781 Block=SLICE_X43Y7 Latch=XQ Net=counter<14>
115Bit 1380986 0x00320200 2810 Block=SLICE_X43Y6 Latch=YQ Net=counter<13>
116Bit 1380989 0x00320200 2813 Block=SLICE_X43Y6 Latch=XQ Net=counter<12>
117Bit 1381018 0x00320200 2842 Block=SLICE_X43Y5 Latch=YQ Net=counter<11>
118Bit 1381021 0x00320200 2845 Block=SLICE_X43Y5 Latch=XQ Net=counter<10>
119Bit 1381050 0x00320200 2874 Block=SLICE_X43Y4 Latch=YQ Net=counter<9>
120Bit 1381053 0x00320200 2877 Block=SLICE_X43Y4 Latch=XQ Net=counter<8>
121Bit 1381082 0x00320200 2906 Block=SLICE_X43Y3 Latch=YQ Net=counter<7>
122Bit 1381085 0x00320200 2909 Block=SLICE_X43Y3 Latch=XQ Net=counter<6>
123Bit 1381114 0x00320200 2938 Block=SLICE_X43Y2 Latch=YQ Net=counter<5>
124Bit 1381117 0x00320200 2941 Block=SLICE_X43Y2 Latch=XQ Net=counter<4>
125Bit 1381146 0x00320200 2970 Block=SLICE_X43Y1 Latch=YQ Net=counter<3>
126Bit 1381149 0x00320200 2973 Block=SLICE_X43Y1 Latch=XQ Net=counter<2>
127Bit 1381178 0x00320200 3002 Block=SLICE_X43Y0 Latch=YQ Net=counter<1>
128Bit 1381181 0x00320200 3005 Block=SLICE_X43Y0 Latch=XQ Net=counter<0>
129Bit 1434781 0x00340000 733 Block=SLICE_X44Y71 Latch=XQ Net=UART/isr1/ISR<0>
130Bit 1434810 0x00340000 762 Block=SLICE_X44Y70 Latch=YQ Net=UART/isr1/ISR<1>
131Bit 1434842 0x00340000 794 Block=SLICE_X44Y69 Latch=YQ Net=UART/isr1/mask_dato_rdy
132Bit 1434877 0x00340000 829 Block=SLICE_X44Y68 Latch=XQ Net=UART/isr1/ISR<2>
133Bit 1434906 0x00340000 858 Block=SLICE_X44Y67 Latch=YQ Net=UART/lcr1/LCR<0>
134Bit 1434909 0x00340000 861 Block=SLICE_X44Y67 Latch=XQ Net=UART/lcr1/LCR<1>
135Bit 1435002 0x00340000 954 Block=SLICE_X44Y64 Latch=YQ Net=UART/lcr1/LCR<4>
136Bit 1435005 0x00340000 957 Block=SLICE_X44Y64 Latch=XQ Net=UART/lcr1/LCR<5>
137Bit 1438010 0x00340200 858 Block=SLICE_X45Y67 Latch=YQ Net=UART/lcr1/LCR<6>
138Bit 1438013 0x00340200 861 Block=SLICE_X45Y67 Latch=XQ Net=UART/lcr1/LCR<7>
139Bit 1438074 0x00340200 922 Block=SLICE_X45Y65 Latch=YQ Net=UART/lcr1/LCR<2>
140Bit 1438077 0x00340200 925 Block=SLICE_X45Y65 Latch=XQ Net=UART/lcr1/LCR<3>
141Bit 1493754 0x00360000 730 Block=SLICE_X46Y71 Latch=YQ Net=UART/isr1/mask_tx_empty
142Bit 1493853 0x00360000 829 Block=SLICE_X46Y68 Latch=XQ Net=UART/dato_rdy1/err_overrun
143Bit 1494202 0x00360000 1178 Block=SLICE_X46Y57 Latch=YQ Net=UART/div27/div27<2>
144Bit 1494205 0x00360000 1181 Block=SLICE_X46Y57 Latch=XQ Net=UART/div27/div27<3>
145Bit 1494234 0x00360000 1210 Block=SLICE_X46Y56 Latch=YQ Net=UART/div27/div27<1>
146Bit 1497309 0x00360200 1181 Block=SLICE_X47Y57 Latch=XQ Net=UART/div27/div27<0>
147Bit 1497341 0x00360200 1213 Block=SLICE_X47Y56 Latch=XQ Net=UART/div27/div27<4>
148Bit 1552730 0x00380000 730 Block=SLICE_X48Y71 Latch=YQ Net=UART/dato_rdy1/dato_rdy
149Bit 1552794 0x00380000 794 Block=SLICE_X48Y69 Latch=YQ Net=UART/div_ms1/div<12>
150Bit 1552797 0x00380000 797 Block=SLICE_X48Y69 Latch=XQ Net=UART/div_ms1/div<13>
151Bit 1552826 0x00380000 826 Block=SLICE_X48Y68 Latch=YQ Net=UART/div_ms1/div<14>
152Bit 1552829 0x00380000 829 Block=SLICE_X48Y68 Latch=XQ Net=UART/div_ms1/div<15>
153Bit 1552922 0x00380000 922 Block=SLICE_X48Y65 Latch=YQ Net=UART/div_ms1/div<6>
154Bit 1552925 0x00380000 925 Block=SLICE_X48Y65 Latch=XQ Net=UART/div_ms1/div<7>
155Bit 1552954 0x00380000 954 Block=SLICE_X48Y64 Latch=YQ Net=UART/div_ms1/div<2>
156Bit 1552957 0x00380000 957 Block=SLICE_X48Y64 Latch=XQ Net=UART/div_ms1/div<3>
157Bit 1553018 0x00380000 1018 Block=SLICE_X48Y62 Latch=YQ Net=UART/div_ms1/clk_out
158Bit 1556285 0x00380200 1181 Block=SLICE_X49Y57 Latch=XQ Net=UART/div27/div27<5>
159Bit 1614554 0x003a0200 474 Block=SLICE_X50Y79 Latch=YQ Net=UART/bufftx1/dato_tx<6>
160Bit 1614557 0x003a0200 477 Block=SLICE_X50Y79 Latch=XQ Net=UART/bufftx1/dato_tx<7>
161Bit 1614618 0x003a0200 538 Block=SLICE_X50Y77 Latch=YQ Net=UART/isr1/aux1
162Bit 1614682 0x003a0200 602 Block=SLICE_X50Y75 Latch=YQ Net=UART/bufftx1/dato_tx<4>
163Bit 1614685 0x003a0200 605 Block=SLICE_X50Y75 Latch=XQ Net=UART/bufftx1/dato_tx<5>
164Bit 1614746 0x003a0200 666 Block=SLICE_X50Y73 Latch=YQ Net=UART/isr1/carga_ISRd
165Bit 1614906 0x003a0200 826 Block=SLICE_X50Y68 Latch=YQ Net=UART/bufftx1/dato_tx<0>
166Bit 1614909 0x003a0200 829 Block=SLICE_X50Y68 Latch=XQ Net=UART/bufftx1/dato_tx<1>
167Bit 1614938 0x003a0200 858 Block=SLICE_X50Y67 Latch=YQ Net=UART/div_ms1/div<4>
168Bit 1614941 0x003a0200 861 Block=SLICE_X50Y67 Latch=XQ Net=UART/div_ms1/div<5>
169Bit 1615002 0x003a0200 922 Block=SLICE_X50Y65 Latch=YQ Net=UART/bufftx1/buftx<1>
170Bit 1615005 0x003a0200 925 Block=SLICE_X50Y65 Latch=XQ Net=UART/bufftx1/buftx<2>
171Bit 1615034 0x003a0200 954 Block=SLICE_X50Y64 Latch=YQ Net=UART/bufftx1/buftx<9>
172Bit 1615098 0x003a0200 1018 Block=SLICE_X50Y62 Latch=YQ Net=UART/muestreo1/flag_rx
173Bit 1617658 0x003a0400 474 Block=SLICE_X51Y79 Latch=YQ Net=we
174Bit 1617661 0x003a0400 477 Block=SLICE_X51Y79 Latch=XQ Net=w_st
175Bit 1617850 0x003a0400 666 Block=SLICE_X51Y73 Latch=YQ Net=UART/bufftx1/buftx<5>
176Bit 1617853 0x003a0400 669 Block=SLICE_X51Y73 Latch=XQ Net=UART/bufftx1/buftx<6>
177Bit 1617882 0x003a0400 698 Block=SLICE_X51Y72 Latch=YQ Net=UART/bufftx1/buftx<7>
178Bit 1617885 0x003a0400 701 Block=SLICE_X51Y72 Latch=XQ Net=UART/bufftx1/buftx<8>
179Bit 1617914 0x003a0400 730 Block=SLICE_X51Y71 Latch=YQ Net=UART/bufftx1/dato_tx<2>
180Bit 1617917 0x003a0400 733 Block=SLICE_X51Y71 Latch=XQ Net=UART/bufftx1/dato_tx<3>
181Bit 1617946 0x003a0400 762 Block=SLICE_X51Y70 Latch=YQ Net=UART/bufftx1/buftx<3>
182Bit 1617949 0x003a0400 765 Block=SLICE_X51Y70 Latch=XQ Net=UART/bufftx1/buftx<4>
183Bit 1617978 0x003a0400 794 Block=SLICE_X51Y69 Latch=YQ Net=UART/ier1/IER<0>
184Bit 1617981 0x003a0400 797 Block=SLICE_X51Y69 Latch=XQ Net=UART/ier1/IER<1>
185Bit 1618010 0x003a0400 826 Block=SLICE_X51Y68 Latch=YQ Net=UART/ier1/IER<2>
186Bit 1618042 0x003a0400 858 Block=SLICE_X51Y67 Latch=YQ Net=UART/div_ms1/div<10>
187Bit 1618045 0x003a0400 861 Block=SLICE_X51Y67 Latch=XQ Net=UART/div_ms1/div<11>
188Bit 1618074 0x003a0400 890 Block=SLICE_X51Y66 Latch=YQ Net=UART/div_ms1/div<8>
189Bit 1618077 0x003a0400 893 Block=SLICE_X51Y66 Latch=XQ Net=UART/div_ms1/div<9>
190Bit 1618106 0x003a0400 922 Block=SLICE_X51Y65 Latch=YQ Net=UART/div_ms1/k_div<2>
191Bit 1618109 0x003a0400 925 Block=SLICE_X51Y65 Latch=XQ Net=UART/div_ms1/k_div<3>
192Bit 1618138 0x003a0400 954 Block=SLICE_X51Y64 Latch=YQ Net=UART/div_ms1/div<0>
193Bit 1618141 0x003a0400 957 Block=SLICE_X51Y64 Latch=XQ Net=UART/div_ms1/div<1>
194Bit 1618202 0x003a0400 1018 Block=SLICE_X51Y62 Latch=YQ Net=UART/pulso1/dff
195Bit 1673850 0x003c0200 794 Block=SLICE_X52Y69 Latch=YQ Net=UART/div_ms1/k_div<12>
196Bit 1673853 0x003c0200 797 Block=SLICE_X52Y69 Latch=XQ Net=UART/div_ms1/k_div<13>
197Bit 1673946 0x003c0200 890 Block=SLICE_X52Y66 Latch=YQ Net=UART/div_ms1/k_div<14>
198Bit 1673949 0x003c0200 893 Block=SLICE_X52Y66 Latch=XQ Net=UART/div_ms1/k_div<15>
199Bit 1673978 0x003c0200 922 Block=SLICE_X52Y65 Latch=YQ Net=UART/div_ms1/k_div<4>
200Bit 1673981 0x003c0200 925 Block=SLICE_X52Y65 Latch=XQ Net=UART/div_ms1/k_div<5>
201Bit 1674010 0x003c0200 954 Block=SLICE_X52Y64 Latch=YQ Net=UART/div_ms1/k_div<0>
202Bit 1674013 0x003c0200 957 Block=SLICE_X52Y64 Latch=XQ Net=UART/div_ms1/k_div<1>
203Bit 1676954 0x02000000 794 Block=SLICE_X53Y69 Latch=YQ Net=UART/div_ms1/k_div<10>
204Bit 1676957 0x02000000 797 Block=SLICE_X53Y69 Latch=XQ Net=UART/div_ms1/k_div<11>
205Bit 1676986 0x02000000 826 Block=SLICE_X53Y68 Latch=YQ Net=UART/div_ms1/k_div<8>
206Bit 1676989 0x02000000 829 Block=SLICE_X53Y68 Latch=XQ Net=UART/div_ms1/k_div<9>
207Bit 1677146 0x02000000 986 Block=SLICE_X53Y63 Latch=YQ Net=UART/div_ms1/k_div<6>
208Bit 1677149 0x02000000 989 Block=SLICE_X53Y63 Latch=XQ Net=UART/div_ms1/k_div<7>
209Bit 1732893 0x02002400 861 Block=SLICE_X54Y67 Latch=XQ Net=UART/ctrl_tx1/tx_empty
210Bit 1732986 0x02002400 954 Block=SLICE_X54Y64 Latch=YQ Net=UART/div161/div16<1>
211Bit 1732989 0x02002400 957 Block=SLICE_X54Y64 Latch=XQ Net=UART/div161/div16<0>
212Bit 1733021 0x02002400 989 Block=SLICE_X54Y63 Latch=XQ Net=UART/ctrl_tx1/tx_on
213Bit 1733050 0x02002400 1018 Block=SLICE_X54Y62 Latch=YQ Net=UART/ctrl_tx1/cont_tx<2>
214Bit 1733053 0x02002400 1021 Block=SLICE_X54Y62 Latch=XQ Net=UART/ctrl_tx1/cont_tx<3>
215Bit 1736058 0x02002600 922 Block=SLICE_X55Y65 Latch=YQ Net=UART/pulso3/dff
216Bit 1736090 0x02002600 954 Block=SLICE_X55Y64 Latch=YQ Net=UART/div161/div16<2>
217Bit 1736093 0x02002600 957 Block=SLICE_X55Y64 Latch=XQ Net=UART/div161/div16<3>
218Bit 1736122 0x02002600 986 Block=SLICE_X55Y63 Latch=YQ Net=UART/ctrl_tx1/cont_tx<0>
219Bit 1736125 0x02002600 989 Block=SLICE_X55Y63 Latch=XQ Net=UART/ctrl_tx1/cont_tx<1>
220Bit 1736378 0x02002600 1242 Block=SLICE_X55Y55 Latch=YQ Net=UART/ifrxd1/ifrxd<2>
221Bit 1736381 0x02002600 1245 Block=SLICE_X55Y55 Latch=XQ Net=UART/ifrxd1/ifrxd<1>
222Bit 2089039 0x02027200 47 Block=P79 Latch=IQ1 Net=buffer_addr<2>
223Bit 2205104 0x04002400 1264 Block=P71 Latch=O2 Net=irq_pin_OBUF
224Bit 2205255 0x04002400 1415 Block=P67 Latch=O2 Net=UART/bufftx1/buftx_0_mux0000
225Bit 2208256 0x04020000 1312 Block=P69 Latch=IQ1 Net=sncs
226Bit 2208335 0x04020000 1391 Block=P68 Latch=IQ1 Net=UART/ifrxd1/ifrxd<0>
227Bit 2211367 0x04020200 1319 Block=P69 Latch=I Net=ncs_IBUF
228

Archive Download this file

Branches:
master



interactive