Root/UART/logic/build/project_r.par

1Release 10.1.03 par K.39 (lin)
2Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
3
4cain-laptop:: Thu Nov 11 14:38:14 2010
5
6par -w project.ncd project_r.ncd
7
8
9Constraints file: project.pcf.
10PMSPEC -- Overriding Xilinx file </opt/cad/Xilinx/10.1/ISE/spartan3e/data/spartan3e.acd> with local file
11</opt/cad/Xilinx/10.1/ISE/spartan3e/data/spartan3e.acd>
12Loading device for application Rf_Device from file '3s500e.nph' in environment
13/opt/cad/Xilinx/10.1/ISE:/opt/cad/Xilinx/10.1/ISE/.
14   "uart_peripheral" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
15
16Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
17Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
18
19INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
20   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
21   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
22   the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
23   balance between the fastest runtime and best performance, set the effort level to "med".
24
25Device speed data version: "PRODUCTION 1.27 2008-01-09".
26
27
28Design Summary Report:
29
30 Number of External IOBs 20 out of 66 30%
31
32   Number of External Input IOBs 9
33
34      Number of External Input IBUFs 9
35        Number of LOCed External Input IBUFs 9 out of 9 100%
36
37
38   Number of External Output IOBs 3
39
40      Number of External Output IOBs 3
41        Number of LOCed External Output IOBs 3 out of 3 100%
42
43
44   Number of External Bidir IOBs 8
45
46      Number of External Bidir IOBs 8
47        Number of LOCed External Bidir IOBs 8 out of 8 100%
48
49
50   Number of BUFGMUXs 1 out of 24 4%
51   Number of Slices 138 out of 4656 2%
52      Number of SLICEMs 0 out of 2328 0%
53
54
55
56Overall effort level (-ol): Standard
57Placer effort level (-pl): High
58Placer cost table entry (-t): 1
59Router effort level (-rl): Standard
60
61
62Starting Placer
63
64Phase 1.1
65Phase 1.1 (Checksum:149c9) REAL time: 9 secs
66
67Phase 2.7
68Phase 2.7 (Checksum:149c9) REAL time: 9 secs
69
70Phase 3.31
71Phase 3.31 (Checksum:149c9) REAL time: 9 secs
72
73Phase 4.2
74
75.
76Phase 4.2 (Checksum:159e9) REAL time: 9 secs
77
78Phase 5.30
79Phase 5.30 (Checksum:159e9) REAL time: 9 secs
80
81Phase 6.8
82.
83.
84.
85.
86.
87Phase 6.8 (Checksum:d4161) REAL time: 21 secs
88
89Phase 7.5
90Phase 7.5 (Checksum:d4161) REAL time: 21 secs
91
92Phase 8.18
93Phase 8.18 (Checksum:d708d) REAL time: 27 secs
94
95Phase 9.5
96Phase 9.5 (Checksum:d708d) REAL time: 27 secs
97
98REAL time consumed by placer: 27 secs
99CPU time consumed by placer: 23 secs
100Writing design to file project_r.ncd
101
102
103Total REAL time to Placer completion: 27 secs
104Total CPU time to Placer completion: 24 secs
105
106Starting Router
107
108Phase 1: 909 unrouted; REAL time: 37 secs
109
110Phase 2: 799 unrouted; REAL time: 37 secs
111
112Phase 3: 166 unrouted; REAL time: 38 secs
113
114Phase 4: 166 unrouted; (241538) REAL time: 38 secs
115
116Phase 5: 167 unrouted; (0) REAL time: 38 secs
117
118Phase 6: 0 unrouted; (0) REAL time: 39 secs
119
120Phase 7: 0 unrouted; (0) REAL time: 39 secs
121
122Phase 8: 0 unrouted; (0) REAL time: 39 secs
123
124Phase 9: 0 unrouted; (0) REAL time: 39 secs
125
126Phase 10: 0 unrouted; (0) REAL time: 40 secs
127
128
129Total REAL time to Router completion: 40 secs
130Total CPU time to Router completion: 36 secs
131
132Partition Implementation Status
133-------------------------------
134
135  No Partitions were found in this design.
136
137-------------------------------
138
139Generating "PAR" statistics.
140
141**************************
142Generating Clock Report
143**************************
144
145+---------------------+--------------+------+------+------------+-------------+
146| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
147+---------------------+--------------+------+------+------------+-------------+
148| clk_BUFGP | BUFGMUX_X2Y1| No | 109 | 0.084 | 0.201 |
149+---------------------+--------------+------+------+------------+-------------+
150
151* Net Skew is the difference between the minimum and maximum routing
152only delays for the net. Note this is different from Clock Skew which
153is reported in TRCE timing report. Clock Skew is the difference between
154the minimum and maximum path delays which includes logic delays.
155
156Timing Score: 0
157
158INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
159   requested value.
160Asterisk (*) preceding a constraint indicates it was not met.
161   This may be due to a setup or hold violation.
162
163------------------------------------------------------------------------------------------------------
164  Constraint | Check | Worst Case | Best Case | Timing | Timing
165                                            | | Slack | Achievable | Errors | Score
166------------------------------------------------------------------------------------------------------
167  Autotimespec constraint for clock net clk | SETUP | N/A| 15.993ns| N/A| 0
168  _BUFGP | HOLD | 1.022ns| | 0| 0
169------------------------------------------------------------------------------------------------------
170
171
172All constraints were met.
173INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
174   constraint does not cover any paths or that it has no requested value.
175
176
177Generating Pad Report.
178
179All signals are completely routed.
180
181Total REAL time to PAR completion: 41 secs
182Total CPU time to PAR completion: 37 secs
183
184Peak Memory Usage: 126 MB
185
186Placement: Completed - No errors found.
187Routing: Completed - No errors found.
188
189Number of error messages: 0
190Number of warning messages: 0
191Number of info messages: 2
192
193Writing design to file project_r.ncd
194
195
196
197PAR done!
198

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