Root/UART/logic/build/project_r.twr

1--------------------------------------------------------------------------------
2Release 10.1.03 Trace (lin)
3Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
4
5/opt/cad/Xilinx/10.1/ISE/bin/lin/unwrapped/trce -v 25 project_r.ncd project.pcf
6
7Design file: project_r.ncd
8Physical constraint file: project.pcf
9Device,package,speed: xc3s500e,vq100,-4 (PRODUCTION 1.27 2008-01-09)
10Report level: verbose report, limited to 25 items per constraint
11
12Environment Variable Effect
13-------------------- ------
14NONE No environment variables were set
15--------------------------------------------------------------------------------
16
17INFO:Timing:2698 - No timing constraints found, doing default enumeration.
18INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
19   option. All paths that are not constrained will be reported in the
20   unconstrained paths section(s) of the report.
21INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
22   a 50 Ohm transmission line loading model. For the details of this model,
23   and for more information on accounting for different loading conditions,
24   please see the device datasheet.
25
26
27
28Data Sheet report:
29-----------------
30All values displayed in nanoseconds (ns)
31
32Setup/Hold to clock clk
33------------+------------+------------+------------------+--------+
34            | Setup to | Hold to | | Clock |
35Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
36------------+------------+------------+------------------+--------+
37RxD | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
38addr<0> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
39addr<1> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
40addr<2> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
41ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
42nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
43reset | 4.649(R)| -0.365(R)|clk_BUFGP | 0.000|
44sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
45sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
46sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
47sram_data<3>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
48sram_data<4>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
49sram_data<5>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
50sram_data<6>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
51sram_data<7>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
52------------+------------+------------+------------------+--------+
53
54Clock clk to Pad
55------------+------------+------------------+--------+
56            | clk (edge) | | Clock |
57Destination | to PAD |Internal Clock(s) | Phase |
58------------+------------+------------------+--------+
59TxD | 6.163(R)|clk_BUFGP | 0.000|
60irq_pin | 10.697(R)|clk_BUFGP | 0.000|
61led | 6.155(R)|clk_BUFGP | 0.000|
62sram_data<0>| 14.532(R)|clk_BUFGP | 0.000|
63            | 16.364(F)|clk_BUFGP | 0.000|
64sram_data<1>| 15.462(R)|clk_BUFGP | 0.000|
65            | 17.685(F)|clk_BUFGP | 0.000|
66sram_data<2>| 15.054(R)|clk_BUFGP | 0.000|
67            | 16.594(F)|clk_BUFGP | 0.000|
68sram_data<3>| 14.794(R)|clk_BUFGP | 0.000|
69            | 16.334(F)|clk_BUFGP | 0.000|
70sram_data<4>| 14.119(R)|clk_BUFGP | 0.000|
71            | 15.659(F)|clk_BUFGP | 0.000|
72sram_data<5>| 15.051(R)|clk_BUFGP | 0.000|
73            | 16.591(F)|clk_BUFGP | 0.000|
74sram_data<6>| 15.120(R)|clk_BUFGP | 0.000|
75            | 16.660(F)|clk_BUFGP | 0.000|
76sram_data<7>| 14.331(R)|clk_BUFGP | 0.000|
77            | 17.406(F)|clk_BUFGP | 0.000|
78------------+------------+------------------+--------+
79
80Clock to Setup on destination clock clk
81---------------+---------+---------+---------+---------+
82               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
83Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
84---------------+---------+---------+---------+---------+
85clk | 9.370| 7.997| | |
86---------------+---------+---------+---------+---------+
87
88Pad to Pad
89---------------+---------------+---------+
90Source Pad |Destination Pad| Delay |
91---------------+---------------+---------+
92ncs |sram_data<0> | 8.998|
93ncs |sram_data<1> | 9.262|
94ncs |sram_data<2> | 8.918|
95ncs |sram_data<3> | 9.517|
96ncs |sram_data<4> | 9.167|
97ncs |sram_data<5> | 8.636|
98ncs |sram_data<6> | 9.866|
99ncs |sram_data<7> | 9.858|
100noe |sram_data<0> | 8.802|
101noe |sram_data<1> | 9.066|
102noe |sram_data<2> | 8.722|
103noe |sram_data<3> | 9.321|
104noe |sram_data<4> | 8.971|
105noe |sram_data<5> | 8.440|
106noe |sram_data<6> | 9.670|
107noe |sram_data<7> | 9.662|
108---------------+---------------+---------+
109
110
111Analysis completed Thu Nov 11 14:39:04 2010
112--------------------------------------------------------------------------------
113
114Trace Settings:
115-------------------------
116Trace Settings
117
118Peak Memory Usage: 93 MB
119
120
121
122

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