Root/UART/logic/build/project_summary.xml

1<?xml version="1.0" encoding="UTF-8"?>
2<!-- IMPORTANT: This is an internal file that has been generated
3     by the Xilinx ISE software. Any direct editing or
4     changes made to this file may result in unpredictable
5     behavior or data corruption. It is strongly advised that
6     users do not edit the contents of this file. -->
7<DesignSummary rev="2">
8<CmdHistory>
9</CmdHistory>
10</DesignSummary>
11

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