Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2	module uart_peripheral(clk, sram_data, addr, nwe, ncs, noe, reset, led, RxD,TxD,irq_pin,RxD2,TxD2);
3	parameter B = (7);
4
5	input clk, nwe, ncs, noe, reset,RxD,RxD2;
6	input [2:0] addr;
7	inout [B:0] sram_data;
8	output led,TxD,TxD2;
9	output irq_pin;
10	wire [6:0] ISRC_LP;
11	// synchronize signals
12	reg sncs, snwe;
13	reg [12:0] buffer_addr;
14	reg [B:0] buffer_data;
15	reg [23:0] counter;
16	// interfaz fpga signals
17	// wire [12:0] addr;
18
19	// bram interfaz signals
20	reg we;
21	reg w_st;
22	wire [7:0] RD;
23	reg [B:0] wdBus;
24	wire [B:0] rdBus;
25	// interefaz signals assignments
26	wire T = ~noe \| ncs;
27	assign sram_data = T?8'bZ:rdBus;
28	assign out=irq_pin;
29	//--------------------------------------------------------------------------
30
31	// synchronize assignment
32	always @(negedge clk)
33	begin
34	sncs <= ncs;
35	snwe <= nwe;
36	buffer_data <= sram_data;
37	buffer_addr <= addr;
38	end
39
40	// write access cpu to bram
41	always @(posedge clk)
42	if(~reset) {w_st, we, wdBus} <= 0;
43	else begin
44	wdBus <= buffer_data;
45	case (w_st)
46	0: begin
47	we <= 0;
48	if(sncs \| snwe) w_st <= 1;
49	end
50	1: begin
51	if(~(sncs \| snwe)) begin
52	we <= 1;
53	w_st <= 0;
54	end
55	else we <= 0;
56	end
57	endcase
58	end
59
60
61
62	//the UART Module
63	UART UART(
64	.CLK(clk),
65	.reset(~reset),
66	.CS(~sncs),
67	.nRW(we),
68	.data_in(wdBus),
69	.data_out(rdBus),
70	.RxD(RxD),
71	.TxD(TxD),
72	.add(buffer_addr),
73	.nIRQ(irq_pin)
74	);
75
76	always @(posedge clk) begin
77	if (~reset)
78	counter <= {24{1'b0}};
79	else
80	counter <= counter + 1;
81	end
82	assign led = counter[23];
83
84
85	endmodule
86

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