Hardware Design: SIE
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Hardware Design: SIE Git Source Tree
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| 1 | DESIGN = uart_peripheral |
| 2 | PINS = $(DESIGN).ucf |
| 3 | DEVICE = xc3s500e-VQ100-4 |
| 4 | BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ |
| 5 | -g CRC:enable -g StartUpClk:CCLK |
| 6 | |
| 7 | SIM_CMD = vsim |
| 8 | SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do |
| 9 | SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) |
| 10 | IVERILOG = iverilog |
| 11 | |
| 12 | SAKC_IP = 192.168.254.101 |
| 13 | |
| 14 | SRC = uart_peripheral.v \ |
| 15 | uart.v |
| 16 | |
| 17 | SIM_SRC =uart_peripheral.v\ |
| 18 | |
| 19 | |
| 20 | all: bits |
| 21 | |
| 22 | remake: clean-build all |
| 23 | |
| 24 | clean: |
| 25 | rm -rf *~ */*~ a.out *.log *.key *.edf *.ps trace.dat |
| 26 | rm -rf *.bit build |
| 27 | |
| 28 | cleanall: clean |
| 29 | rm -rf build simulation/work simulation/transcript simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd |
| 30 | |
| 31 | bits: $(DESIGN).bit |
| 32 | |
| 33 | # |
| 34 | # Synthesis |
| 35 | # |
| 36 | build/project.src: |
| 37 | @[ -d build ] || mkdir build |
| 38 | @rm -f $@ |
| 39 | for i in $(SRC); do echo verilog work ../$$i >> $@; done |
| 40 | for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done |
| 41 | |
| 42 | build/project.xst: build/project.src |
| 43 | echo "run" > $@ |
| 44 | echo "-top $(DESIGN) " >> $@ |
| 45 | echo "-p $(DEVICE)" >> $@ |
| 46 | echo "-opt_mode Area" >> $@ |
| 47 | echo "-opt_level 1" >> $@ |
| 48 | echo "-ifn project.src" >> $@ |
| 49 | echo "-ifmt mixed" >> $@ |
| 50 | echo "-ofn project.ngc" >> $@ |
| 51 | echo "-ofmt NGC" >> $@ |
| 52 | echo "-rtlview yes" >> $@ |
| 53 | |
| 54 | build/project.ngc: build/project.xst $(SRC) |
| 55 | cd build && xst -ifn project.xst -ofn project.log |
| 56 | |
| 57 | build/project.ngd: build/project.ngc $(PINS) |
| 58 | cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS) |
| 59 | |
| 60 | build/project.ncd: build/project.ngd |
| 61 | cd build && map -pr b -p $(DEVICE) project |
| 62 | |
| 63 | build/project_r.ncd: build/project.ncd |
| 64 | cd build && par -w project project_r.ncd |
| 65 | |
| 66 | build/project_r.twr: build/project_r.ncd |
| 67 | cd build && trce -v 25 project_r.ncd project.pcf |
| 68 | |
| 69 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr |
| 70 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) |
| 71 | @mv -f build/project_r.bit $@ |
| 72 | |
| 73 | build/project_r.v: build/project_r.ncd |
| 74 | cd build && ngd2ver project.ngd -w project.v |
| 75 | |
| 76 | modelsim: |
| 77 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
| 78 | |
| 79 | timesim: build/project_r.v |
| 80 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do |
| 81 | |
| 82 | iversim: |
| 83 | $(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB |
| 84 | vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/ |
| 85 | gtkwave simulation/$(DESIGN)_TB.vcd& |
| 86 | |
| 87 | upload: $(DESIGN).bit |
| 88 | scp $(DESIGN).bit root@$(SAKC_IP):binaries |
| 89 |
Branches:
master
